This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
233 lines
6.6 KiB
C++
233 lines
6.6 KiB
C++
/*
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* RISC-V translation routines for the RV64A Standard Extension.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
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{
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TCGv src1 = tcg_temp_new();
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/* Put addr in load_res, data in load_val. */
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gen_get_gpr(src1, a->rs1);
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if (a->rl) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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}
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tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
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if (a->aq) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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}
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tcg_gen_mov_tl(load_res, src1);
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gen_set_gpr(a->rd, load_val);
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tcg_temp_free(src1);
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return true;
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}
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static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
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{
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TCGv src1 = tcg_temp_new();
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TCGv src2 = tcg_temp_new();
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TCGv dat = tcg_temp_new();
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TCGLabel *l1 = gen_new_label();
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TCGLabel *l2 = gen_new_label();
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gen_get_gpr(src1, a->rs1);
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tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
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gen_get_gpr(src2, a->rs2);
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/*
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* Note that the TCG atomic primitives are SC,
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* so we can ignore AQ/RL along this path.
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*/
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tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
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ctx->mem_idx, mop);
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tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
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gen_set_gpr(a->rd, dat);
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tcg_gen_br(l2);
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gen_set_label(l1);
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/*
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* Address comparison failure. However, we still need to
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* provide the memory barrier implied by AQ/RL.
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*/
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tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
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tcg_gen_movi_tl(dat, 1);
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gen_set_gpr(a->rd, dat);
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gen_set_label(l2);
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/*
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* Clear the load reservation, since an SC must fail if there is
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* an SC to any address, in between an LR and SC pair.
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*/
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tcg_gen_movi_tl(load_res, -1);
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tcg_temp_free(dat);
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tcg_temp_free(src1);
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tcg_temp_free(src2);
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return true;
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}
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static bool gen_amo(DisasContext *ctx, arg_atomic *a,
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void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
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MemOp mop)
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{
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TCGv src1 = tcg_temp_new();
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TCGv src2 = tcg_temp_new();
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gen_get_gpr(src1, a->rs1);
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gen_get_gpr(src2, a->rs2);
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(*func)(src2, src1, src2, ctx->mem_idx, mop);
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gen_set_gpr(a->rd, src2);
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tcg_temp_free(src1);
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tcg_temp_free(src2);
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return true;
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}
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static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
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}
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static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
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}
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static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
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}
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static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
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}
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static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
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}
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static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
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}
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static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
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}
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static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
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}
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static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
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}
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static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
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}
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static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
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{
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REQUIRE_EXT(ctx, RVA);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
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}
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static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
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}
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static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
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}
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static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
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}
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static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
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}
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static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
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}
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static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
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}
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static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
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}
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static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
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}
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static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
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}
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static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
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}
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static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
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}
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