renesas_tmr: 8bit timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200224141923.82118-16-ysato@users.sourceforge.jp> [PMD: Split from CMT, filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
478 lines
13 KiB
C
478 lines
13 KiB
C
/*
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* Renesas 8bit timer
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*
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* Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
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* (Rev.1.40 R01UH0033EJ0140)
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*
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* Copyright (c) 2019 Yoshinori Sato
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/registerfields.h"
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#include "hw/qdev-properties.h"
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#include "hw/timer/renesas_tmr.h"
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#include "migration/vmstate.h"
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REG8(TCR, 0)
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FIELD(TCR, CCLR, 3, 2)
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FIELD(TCR, OVIE, 5, 1)
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FIELD(TCR, CMIEA, 6, 1)
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FIELD(TCR, CMIEB, 7, 1)
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REG8(TCSR, 2)
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FIELD(TCSR, OSA, 0, 2)
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FIELD(TCSR, OSB, 2, 2)
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FIELD(TCSR, ADTE, 4, 2)
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REG8(TCORA, 4)
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REG8(TCORB, 6)
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REG8(TCNT, 8)
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REG8(TCCR, 10)
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FIELD(TCCR, CKS, 0, 3)
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FIELD(TCCR, CSS, 3, 2)
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FIELD(TCCR, TMRIS, 7, 1)
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#define INTERNAL 0x01
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#define CASCADING 0x03
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#define CCLR_A 0x01
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#define CCLR_B 0x02
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static const int clkdiv[] = {0, 1, 2, 8, 32, 64, 1024, 8192};
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static uint8_t concat_reg(uint8_t *reg)
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{
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return (reg[0] << 8) | reg[1];
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}
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static void update_events(RTMRState *tmr, int ch)
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{
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uint16_t diff[TMR_NR_EVENTS], min;
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int64_t next_time;
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int i, event;
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if (tmr->tccr[ch] == 0) {
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return ;
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}
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if (FIELD_EX8(tmr->tccr[ch], TCCR, CSS) == 0) {
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/* external clock mode */
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/* event not happened */
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return ;
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}
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if (FIELD_EX8(tmr->tccr[0], TCCR, CSS) == CASCADING) {
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/* cascading mode */
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if (ch == 1) {
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tmr->next[ch] = none;
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return ;
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}
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diff[cmia] = concat_reg(tmr->tcora) - concat_reg(tmr->tcnt);
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diff[cmib] = concat_reg(tmr->tcorb) - concat_reg(tmr->tcnt);
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diff[ovi] = 0x10000 - concat_reg(tmr->tcnt);
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} else {
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/* separate mode */
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diff[cmia] = tmr->tcora[ch] - tmr->tcnt[ch];
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diff[cmib] = tmr->tcorb[ch] - tmr->tcnt[ch];
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diff[ovi] = 0x100 - tmr->tcnt[ch];
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}
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/* Search for the most recently occurring event. */
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for (event = 0, min = diff[0], i = 1; i < none; i++) {
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if (min > diff[i]) {
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event = i;
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min = diff[i];
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}
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}
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tmr->next[ch] = event;
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next_time = diff[event];
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next_time *= clkdiv[FIELD_EX8(tmr->tccr[ch], TCCR, CKS)];
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next_time *= NANOSECONDS_PER_SECOND;
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next_time /= tmr->input_freq;
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next_time += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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timer_mod(&tmr->timer[ch], next_time);
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}
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static int elapsed_time(RTMRState *tmr, int ch, int64_t delta)
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{
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int divrate = clkdiv[FIELD_EX8(tmr->tccr[ch], TCCR, CKS)];
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int et;
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tmr->div_round[ch] += delta;
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if (divrate > 0) {
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et = tmr->div_round[ch] / divrate;
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tmr->div_round[ch] %= divrate;
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} else {
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/* disble clock. so no update */
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et = 0;
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}
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return et;
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}
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static uint16_t read_tcnt(RTMRState *tmr, unsigned size, int ch)
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{
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int64_t delta, now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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int elapsed, ovf = 0;
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uint16_t tcnt[2];
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uint32_t ret;
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delta = (now - tmr->tick) * NANOSECONDS_PER_SECOND / tmr->input_freq;
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if (delta > 0) {
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tmr->tick = now;
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if (FIELD_EX8(tmr->tccr[1], TCCR, CSS) == INTERNAL) {
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/* timer1 count update */
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elapsed = elapsed_time(tmr, 1, delta);
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if (elapsed >= 0x100) {
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ovf = elapsed >> 8;
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}
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tcnt[1] = tmr->tcnt[1] + (elapsed & 0xff);
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}
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switch (FIELD_EX8(tmr->tccr[0], TCCR, CSS)) {
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case INTERNAL:
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elapsed = elapsed_time(tmr, 0, delta);
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tcnt[0] = tmr->tcnt[0] + elapsed;
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break;
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case CASCADING:
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if (ovf > 0) {
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tcnt[0] = tmr->tcnt[0] + ovf;
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}
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break;
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}
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} else {
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tcnt[0] = tmr->tcnt[0];
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tcnt[1] = tmr->tcnt[1];
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}
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if (size == 1) {
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return tcnt[ch];
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} else {
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ret = 0;
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ret = deposit32(ret, 0, 8, tcnt[1]);
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ret = deposit32(ret, 8, 8, tcnt[0]);
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return ret;
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}
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}
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static uint8_t read_tccr(uint8_t r)
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{
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uint8_t tccr = 0;
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tccr = FIELD_DP8(tccr, TCCR, TMRIS,
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FIELD_EX8(r, TCCR, TMRIS));
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tccr = FIELD_DP8(tccr, TCCR, CSS,
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FIELD_EX8(r, TCCR, CSS));
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tccr = FIELD_DP8(tccr, TCCR, CKS,
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FIELD_EX8(r, TCCR, CKS));
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return tccr;
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}
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static uint64_t tmr_read(void *opaque, hwaddr addr, unsigned size)
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{
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RTMRState *tmr = opaque;
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int ch = addr & 1;
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uint64_t ret;
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if (size == 2 && (ch != 0 || addr == A_TCR || addr == A_TCSR)) {
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qemu_log_mask(LOG_GUEST_ERROR, "renesas_tmr: Invalid read size 0x%"
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HWADDR_PRIX "\n",
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addr);
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return UINT64_MAX;
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}
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switch (addr & 0x0e) {
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case A_TCR:
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ret = 0;
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ret = FIELD_DP8(ret, TCR, CCLR,
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FIELD_EX8(tmr->tcr[ch], TCR, CCLR));
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ret = FIELD_DP8(ret, TCR, OVIE,
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FIELD_EX8(tmr->tcr[ch], TCR, OVIE));
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ret = FIELD_DP8(ret, TCR, CMIEA,
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FIELD_EX8(tmr->tcr[ch], TCR, CMIEA));
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ret = FIELD_DP8(ret, TCR, CMIEB,
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FIELD_EX8(tmr->tcr[ch], TCR, CMIEB));
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return ret;
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case A_TCSR:
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ret = 0;
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ret = FIELD_DP8(ret, TCSR, OSA,
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FIELD_EX8(tmr->tcsr[ch], TCSR, OSA));
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ret = FIELD_DP8(ret, TCSR, OSB,
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FIELD_EX8(tmr->tcsr[ch], TCSR, OSB));
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switch (ch) {
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case 0:
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ret = FIELD_DP8(ret, TCSR, ADTE,
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FIELD_EX8(tmr->tcsr[ch], TCSR, ADTE));
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break;
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case 1: /* CH1 ADTE unimplement always 1 */
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ret = FIELD_DP8(ret, TCSR, ADTE, 1);
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break;
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}
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return ret;
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case A_TCORA:
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if (size == 1) {
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return tmr->tcora[ch];
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} else if (ch == 0) {
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return concat_reg(tmr->tcora);
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}
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case A_TCORB:
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if (size == 1) {
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return tmr->tcorb[ch];
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} else {
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return concat_reg(tmr->tcorb);
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}
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case A_TCNT:
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return read_tcnt(tmr, size, ch);
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case A_TCCR:
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if (size == 1) {
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return read_tccr(tmr->tccr[ch]);
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} else {
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return read_tccr(tmr->tccr[0]) << 8 | read_tccr(tmr->tccr[1]);
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}
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default:
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qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX
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" not implemented\n",
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addr);
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break;
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}
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return UINT64_MAX;
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}
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static void tmr_write_count(RTMRState *tmr, int ch, unsigned size,
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uint8_t *reg, uint64_t val)
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{
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if (size == 1) {
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reg[ch] = val;
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update_events(tmr, ch);
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} else {
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reg[0] = extract32(val, 8, 8);
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reg[1] = extract32(val, 0, 8);
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update_events(tmr, 0);
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update_events(tmr, 1);
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}
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}
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static void tmr_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
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{
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RTMRState *tmr = opaque;
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int ch = addr & 1;
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if (size == 2 && (ch != 0 || addr == A_TCR || addr == A_TCSR)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"renesas_tmr: Invalid write size 0x%" HWADDR_PRIX "\n",
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addr);
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return;
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}
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switch (addr & 0x0e) {
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case A_TCR:
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tmr->tcr[ch] = val;
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break;
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case A_TCSR:
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tmr->tcsr[ch] = val;
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break;
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case A_TCORA:
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tmr_write_count(tmr, ch, size, tmr->tcora, val);
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break;
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case A_TCORB:
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tmr_write_count(tmr, ch, size, tmr->tcorb, val);
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break;
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case A_TCNT:
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tmr_write_count(tmr, ch, size, tmr->tcnt, val);
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break;
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case A_TCCR:
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tmr_write_count(tmr, ch, size, tmr->tccr, val);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX
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" not implemented\n",
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addr);
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break;
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}
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}
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static const MemoryRegionOps tmr_ops = {
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.write = tmr_write,
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.read = tmr_read,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 2,
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},
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.valid = {
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.min_access_size = 1,
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.max_access_size = 2,
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},
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};
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static void timer_events(RTMRState *tmr, int ch);
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static uint16_t issue_event(RTMRState *tmr, int ch, int sz,
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uint16_t tcnt, uint16_t tcora, uint16_t tcorb)
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{
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uint16_t ret = tcnt;
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switch (tmr->next[ch]) {
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case none:
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break;
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case cmia:
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if (tcnt >= tcora) {
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if (FIELD_EX8(tmr->tcr[ch], TCR, CCLR) == CCLR_A) {
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ret = tcnt - tcora;
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}
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if (FIELD_EX8(tmr->tcr[ch], TCR, CMIEA)) {
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qemu_irq_pulse(tmr->cmia[ch]);
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}
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if (sz == 8 && ch == 0 &&
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FIELD_EX8(tmr->tccr[1], TCCR, CSS) == CASCADING) {
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tmr->tcnt[1]++;
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timer_events(tmr, 1);
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}
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}
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break;
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case cmib:
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if (tcnt >= tcorb) {
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if (FIELD_EX8(tmr->tcr[ch], TCR, CCLR) == CCLR_B) {
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ret = tcnt - tcorb;
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}
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if (FIELD_EX8(tmr->tcr[ch], TCR, CMIEB)) {
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qemu_irq_pulse(tmr->cmib[ch]);
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}
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}
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break;
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case ovi:
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if ((tcnt >= (1 << sz)) && FIELD_EX8(tmr->tcr[ch], TCR, OVIE)) {
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qemu_irq_pulse(tmr->ovi[ch]);
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}
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break;
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default:
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g_assert_not_reached();
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}
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return ret;
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}
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static void timer_events(RTMRState *tmr, int ch)
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{
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uint16_t tcnt;
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tmr->tcnt[ch] = read_tcnt(tmr, 1, ch);
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if (FIELD_EX8(tmr->tccr[0], TCCR, CSS) != CASCADING) {
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tmr->tcnt[ch] = issue_event(tmr, ch, 8,
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tmr->tcnt[ch],
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tmr->tcora[ch],
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tmr->tcorb[ch]) & 0xff;
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} else {
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if (ch == 1) {
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return ;
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}
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tcnt = issue_event(tmr, ch, 16,
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concat_reg(tmr->tcnt),
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concat_reg(tmr->tcora),
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concat_reg(tmr->tcorb));
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tmr->tcnt[0] = (tcnt >> 8) & 0xff;
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tmr->tcnt[1] = tcnt & 0xff;
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}
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update_events(tmr, ch);
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}
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static void timer_event0(void *opaque)
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{
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RTMRState *tmr = opaque;
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timer_events(tmr, 0);
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}
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static void timer_event1(void *opaque)
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{
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RTMRState *tmr = opaque;
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timer_events(tmr, 1);
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}
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static void rtmr_reset(DeviceState *dev)
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{
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RTMRState *tmr = RTMR(dev);
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tmr->tcr[0] = tmr->tcr[1] = 0x00;
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tmr->tcsr[0] = 0x00;
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tmr->tcsr[1] = 0x10;
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tmr->tcnt[0] = tmr->tcnt[1] = 0x00;
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tmr->tcora[0] = tmr->tcora[1] = 0xff;
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tmr->tcorb[0] = tmr->tcorb[1] = 0xff;
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tmr->tccr[0] = tmr->tccr[1] = 0x00;
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tmr->next[0] = tmr->next[1] = none;
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tmr->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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}
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static void rtmr_init(Object *obj)
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{
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SysBusDevice *d = SYS_BUS_DEVICE(obj);
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RTMRState *tmr = RTMR(obj);
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int i;
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memory_region_init_io(&tmr->memory, OBJECT(tmr), &tmr_ops,
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tmr, "renesas-tmr", 0x10);
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sysbus_init_mmio(d, &tmr->memory);
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for (i = 0; i < ARRAY_SIZE(tmr->ovi); i++) {
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sysbus_init_irq(d, &tmr->cmia[i]);
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sysbus_init_irq(d, &tmr->cmib[i]);
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sysbus_init_irq(d, &tmr->ovi[i]);
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}
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timer_init_ns(&tmr->timer[0], QEMU_CLOCK_VIRTUAL, timer_event0, tmr);
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timer_init_ns(&tmr->timer[1], QEMU_CLOCK_VIRTUAL, timer_event1, tmr);
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}
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static const VMStateDescription vmstate_rtmr = {
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.name = "rx-tmr",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_INT64(tick, RTMRState),
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VMSTATE_UINT8_ARRAY(tcnt, RTMRState, TMR_CH),
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VMSTATE_UINT8_ARRAY(tcora, RTMRState, TMR_CH),
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VMSTATE_UINT8_ARRAY(tcorb, RTMRState, TMR_CH),
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VMSTATE_UINT8_ARRAY(tcr, RTMRState, TMR_CH),
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VMSTATE_UINT8_ARRAY(tccr, RTMRState, TMR_CH),
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VMSTATE_UINT8_ARRAY(tcor, RTMRState, TMR_CH),
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VMSTATE_UINT8_ARRAY(tcsr, RTMRState, TMR_CH),
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VMSTATE_INT64_ARRAY(div_round, RTMRState, TMR_CH),
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VMSTATE_UINT8_ARRAY(next, RTMRState, TMR_CH),
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VMSTATE_TIMER_ARRAY(timer, RTMRState, TMR_CH),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property rtmr_properties[] = {
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DEFINE_PROP_UINT64("input-freq", RTMRState, input_freq, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void rtmr_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->vmsd = &vmstate_rtmr;
|
|
dc->reset = rtmr_reset;
|
|
device_class_set_props(dc, rtmr_properties);
|
|
}
|
|
|
|
static const TypeInfo rtmr_info = {
|
|
.name = TYPE_RENESAS_TMR,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(RTMRState),
|
|
.instance_init = rtmr_init,
|
|
.class_init = rtmr_class_init,
|
|
};
|
|
|
|
static void rtmr_register_types(void)
|
|
{
|
|
type_register_static(&rtmr_info);
|
|
}
|
|
|
|
type_init(rtmr_register_types)
|