Specific xtensa processor overlay for GDB contains register map in the gdb/xtensa-config.c. This description is used by the GDB to e.g. parse 'g' response packets and it may be reused in the qemu's gdbstub (only XTREG definitions for non-pseudoregisters are needed). Currently mainline GDB does not support operations with privileged SRs (see http://sourceware.org/ml/gdb/2011-07/msg00075.html). This support may be enabled, see NUM_CORE_REGS comment in the gdbstub.c Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
371 lines
9.5 KiB
C
371 lines
9.5 KiB
C
/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_XTENSA_H
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#define CPU_XTENSA_H
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#define TARGET_LONG_BITS 32
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#define ELF_MACHINE EM_XTENSA
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#define CPUState struct CPUXtensaState
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#include "config.h"
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#include "qemu-common.h"
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#include "cpu-defs.h"
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#define TARGET_HAS_ICE 1
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#define NB_MMU_MODES 4
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#define TARGET_PAGE_BITS 12
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enum {
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/* Additional instructions */
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XTENSA_OPTION_CODE_DENSITY,
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XTENSA_OPTION_LOOP,
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XTENSA_OPTION_EXTENDED_L32R,
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XTENSA_OPTION_16_BIT_IMUL,
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XTENSA_OPTION_32_BIT_IMUL,
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XTENSA_OPTION_32_BIT_IDIV,
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XTENSA_OPTION_MAC16,
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XTENSA_OPTION_MISC_OP,
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XTENSA_OPTION_COPROCESSOR,
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XTENSA_OPTION_BOOLEAN,
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XTENSA_OPTION_FP_COPROCESSOR,
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XTENSA_OPTION_MP_SYNCHRO,
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XTENSA_OPTION_CONDITIONAL_STORE,
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/* Interrupts and exceptions */
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XTENSA_OPTION_EXCEPTION,
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XTENSA_OPTION_RELOCATABLE_VECTOR,
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XTENSA_OPTION_UNALIGNED_EXCEPTION,
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XTENSA_OPTION_INTERRUPT,
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XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
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XTENSA_OPTION_TIMER_INTERRUPT,
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/* Local memory */
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XTENSA_OPTION_ICACHE,
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XTENSA_OPTION_ICACHE_TEST,
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XTENSA_OPTION_ICACHE_INDEX_LOCK,
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XTENSA_OPTION_DCACHE,
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XTENSA_OPTION_DCACHE_TEST,
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XTENSA_OPTION_DCACHE_INDEX_LOCK,
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XTENSA_OPTION_IRAM,
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XTENSA_OPTION_IROM,
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XTENSA_OPTION_DRAM,
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XTENSA_OPTION_DROM,
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XTENSA_OPTION_XLMI,
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XTENSA_OPTION_HW_ALIGNMENT,
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XTENSA_OPTION_MEMORY_ECC_PARITY,
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/* Memory protection and translation */
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XTENSA_OPTION_REGION_PROTECTION,
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XTENSA_OPTION_REGION_TRANSLATION,
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XTENSA_OPTION_MMU,
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/* Other */
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XTENSA_OPTION_WINDOWED_REGISTER,
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XTENSA_OPTION_PROCESSOR_INTERFACE,
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XTENSA_OPTION_MISC_SR,
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XTENSA_OPTION_THREAD_POINTER,
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XTENSA_OPTION_PROCESSOR_ID,
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XTENSA_OPTION_DEBUG,
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XTENSA_OPTION_TRACE_PORT,
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};
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enum {
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THREADPTR = 231,
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FCR = 232,
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FSR = 233,
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};
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enum {
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LBEG = 0,
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LEND = 1,
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LCOUNT = 2,
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SAR = 3,
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LITBASE = 5,
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SCOMPARE1 = 12,
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WINDOW_BASE = 72,
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WINDOW_START = 73,
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EPC1 = 177,
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DEPC = 192,
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EPS2 = 194,
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EXCSAVE1 = 209,
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CPENABLE = 224,
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INTSET = 226,
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INTCLEAR = 227,
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INTENABLE = 228,
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PS = 230,
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VECBASE = 231,
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EXCCAUSE = 232,
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CCOUNT = 234,
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PRID = 235,
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EXCVADDR = 238,
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CCOMPARE = 240,
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};
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#define PS_INTLEVEL 0xf
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#define PS_INTLEVEL_SHIFT 0
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#define PS_EXCM 0x10
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#define PS_UM 0x20
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#define PS_RING 0xc0
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#define PS_RING_SHIFT 6
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#define PS_OWB 0xf00
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#define PS_OWB_SHIFT 8
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#define PS_CALLINC 0x30000
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#define PS_CALLINC_SHIFT 16
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#define PS_CALLINC_LEN 2
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#define PS_WOE 0x40000
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#define MAX_NAREG 64
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#define MAX_NINTERRUPT 32
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#define MAX_NLEVEL 6
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#define MAX_NNMI 1
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#define MAX_NCCOMPARE 3
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enum {
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/* Static vectors */
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EXC_RESET,
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EXC_MEMORY_ERROR,
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/* Dynamic vectors */
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EXC_WINDOW_OVERFLOW4,
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EXC_WINDOW_UNDERFLOW4,
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EXC_WINDOW_OVERFLOW8,
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EXC_WINDOW_UNDERFLOW8,
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EXC_WINDOW_OVERFLOW12,
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EXC_WINDOW_UNDERFLOW12,
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EXC_IRQ,
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EXC_KERNEL,
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EXC_USER,
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EXC_DOUBLE,
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EXC_MAX
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};
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enum {
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ILLEGAL_INSTRUCTION_CAUSE = 0,
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SYSCALL_CAUSE,
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INSTRUCTION_FETCH_ERROR_CAUSE,
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LOAD_STORE_ERROR_CAUSE,
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LEVEL1_INTERRUPT_CAUSE,
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ALLOCA_CAUSE,
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INTEGER_DIVIDE_BY_ZERO_CAUSE,
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PRIVILEGED_CAUSE = 8,
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LOAD_STORE_ALIGNMENT_CAUSE,
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INSTR_PIF_DATA_ERROR_CAUSE = 12,
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LOAD_STORE_PIF_DATA_ERROR_CAUSE,
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INSTR_PIF_ADDR_ERROR_CAUSE,
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LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
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INST_TLB_MISS_CAUSE,
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INST_TLB_MULTI_HIT_CAUSE,
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INST_FETCH_PRIVILEGE_CAUSE,
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INST_FETCH_PROHIBITED_CAUSE = 20,
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LOAD_STORE_TLB_MISS_CAUSE = 24,
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LOAD_STORE_TLB_MULTI_HIT_CAUSE,
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LOAD_STORE_PRIVILEGE_CAUSE,
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LOAD_PROHIBITED_CAUSE = 28,
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STORE_PROHIBITED_CAUSE,
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COPROCESSOR0_DISABLED = 32,
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};
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typedef enum {
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INTTYPE_LEVEL,
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INTTYPE_EDGE,
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INTTYPE_NMI,
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INTTYPE_SOFTWARE,
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INTTYPE_TIMER,
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INTTYPE_DEBUG,
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INTTYPE_WRITE_ERR,
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INTTYPE_MAX
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} interrupt_type;
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typedef struct XtensaGdbReg {
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int targno;
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int type;
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int group;
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} XtensaGdbReg;
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typedef struct XtensaGdbRegmap {
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int num_regs;
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int num_core_regs;
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/* PC + a + ar + sr + ur */
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XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
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} XtensaGdbRegmap;
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typedef struct XtensaConfig {
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const char *name;
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uint64_t options;
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XtensaGdbRegmap gdb_regmap;
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unsigned nareg;
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int excm_level;
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int ndepc;
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uint32_t vecbase;
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uint32_t exception_vector[EXC_MAX];
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unsigned ninterrupt;
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unsigned nlevel;
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uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
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uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
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uint32_t inttype_mask[INTTYPE_MAX];
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struct {
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uint32_t level;
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interrupt_type inttype;
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} interrupt[MAX_NINTERRUPT];
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unsigned nccompare;
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uint32_t timerint[MAX_NCCOMPARE];
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uint32_t clock_freq_khz;
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} XtensaConfig;
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typedef struct CPUXtensaState {
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const XtensaConfig *config;
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uint32_t regs[16];
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uint32_t pc;
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uint32_t sregs[256];
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uint32_t uregs[256];
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uint32_t phys_regs[MAX_NAREG];
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int pending_irq_level; /* level of last raised IRQ */
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void **irq_inputs;
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QEMUTimer *ccompare_timer;
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uint32_t wake_ccount;
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int64_t halt_clock;
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int exception_taken;
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CPU_COMMON
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} CPUXtensaState;
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#define cpu_init cpu_xtensa_init
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#define cpu_exec cpu_xtensa_exec
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#define cpu_gen_code cpu_xtensa_gen_code
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#define cpu_signal_handler cpu_xtensa_signal_handler
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#define cpu_list xtensa_cpu_list
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CPUXtensaState *cpu_xtensa_init(const char *cpu_model);
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void xtensa_translate_init(void);
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int cpu_xtensa_exec(CPUXtensaState *s);
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void do_interrupt(CPUXtensaState *s);
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void check_interrupts(CPUXtensaState *s);
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void xtensa_irq_init(CPUState *env);
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void xtensa_advance_ccount(CPUState *env, uint32_t d);
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void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active);
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int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
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void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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void xtensa_sync_window_from_phys(CPUState *env);
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void xtensa_sync_phys_from_window(CPUState *env);
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#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
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static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
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{
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return (config->options & XTENSA_OPTION_BIT(opt)) != 0;
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}
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static inline int xtensa_get_cintlevel(const CPUState *env)
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{
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int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
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if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
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level = env->config->excm_level;
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}
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return level;
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}
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static inline int xtensa_get_ring(const CPUState *env)
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{
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
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return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
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} else {
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return 0;
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}
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}
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static inline int xtensa_get_cring(const CPUState *env)
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{
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
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(env->sregs[PS] & PS_EXCM) == 0) {
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return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
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} else {
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return 0;
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}
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}
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _ring0
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#define MMU_MODE1_SUFFIX _ring1
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#define MMU_MODE2_SUFFIX _ring2
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#define MMU_MODE3_SUFFIX _ring3
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static inline int cpu_mmu_index(CPUState *env)
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{
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return xtensa_get_cring(env);
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}
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#define XTENSA_TBFLAG_RING_MASK 0x3
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#define XTENSA_TBFLAG_EXCM 0x4
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#define XTENSA_TBFLAG_LITBASE 0x8
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = 0;
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*flags |= xtensa_get_ring(env);
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if (env->sregs[PS] & PS_EXCM) {
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*flags |= XTENSA_TBFLAG_EXCM;
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}
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
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(env->sregs[LITBASE] & 1)) {
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*flags |= XTENSA_TBFLAG_LITBASE;
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}
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}
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#include "cpu-all.h"
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#include "exec-all.h"
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static inline int cpu_has_work(CPUState *env)
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{
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return env->pending_irq_level;
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}
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static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
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{
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env->pc = tb->pc;
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}
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#endif
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