Embed child devices and replace SysBus initfn with realizefn. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
289 lines
9.3 KiB
C
289 lines
9.3 KiB
C
/*
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* ARM11MPCore internal peripheral emulation.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "hw/sysbus.h"
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#include "hw/misc/arm11scu.h"
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#include "hw/intc/arm_gic.h"
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#include "hw/timer/arm_mptimer.h"
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#include "qemu/timer.h"
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/* MPCore private memory region. */
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#define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv"
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#define ARM11MPCORE_PRIV(obj) \
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OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV)
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typedef struct ARM11MPCorePriveState {
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SysBusDevice parent_obj;
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uint32_t num_cpu;
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MemoryRegion container;
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uint32_t num_irq;
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ARM11SCUState scu;
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GICState gic;
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ARMMPTimerState mptimer;
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ARMMPTimerState wdtimer;
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} ARM11MPCorePriveState;
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/* Per-CPU private memory mapped IO. */
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static void mpcore_priv_set_irq(void *opaque, int irq, int level)
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{
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ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
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qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
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}
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static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
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{
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int i;
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SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu);
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DeviceState *gicdev = DEVICE(&s->gic);
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SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic);
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SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer);
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SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer);
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(scubusdev, 0));
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/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
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* at 0x200, 0x300...
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*/
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for (i = 0; i < (s->num_cpu + 1); i++) {
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hwaddr offset = 0x100 + (i * 0x100);
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memory_region_add_subregion(&s->container, offset,
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sysbus_mmio_get_region(gicbusdev, i + 1));
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}
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/* Add the regions for timer and watchdog for "current CPU" and
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* for each specific CPU.
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*/
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for (i = 0; i < (s->num_cpu + 1); i++) {
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/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
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hwaddr offset = 0x600 + i * 0x100;
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memory_region_add_subregion(&s->container, offset,
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sysbus_mmio_get_region(timerbusdev, i));
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memory_region_add_subregion(&s->container, offset + 0x20,
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sysbus_mmio_get_region(wdtbusdev, i));
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}
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memory_region_add_subregion(&s->container, 0x1000,
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sysbus_mmio_get_region(gicbusdev, 0));
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/* Wire up the interrupt from each watchdog and timer.
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* For each core the timer is PPI 29 and the watchdog PPI 30.
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*/
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for (i = 0; i < s->num_cpu; i++) {
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int ppibase = (s->num_irq - 32) + i * 32;
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sysbus_connect_irq(timerbusdev, i,
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qdev_get_gpio_in(gicdev, ppibase + 29));
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sysbus_connect_irq(wdtbusdev, i,
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qdev_get_gpio_in(gicdev, ppibase + 30));
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}
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}
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static void mpcore_priv_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
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DeviceState *scudev = DEVICE(&s->scu);
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DeviceState *gicdev = DEVICE(&s->gic);
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DeviceState *mptimerdev = DEVICE(&s->mptimer);
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DeviceState *wdtimerdev = DEVICE(&s->wdtimer);
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Error *err = NULL;
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qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
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object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
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qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
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object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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/* Pass through outbound IRQ lines from the GIC */
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sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic));
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/* Pass through inbound GPIO lines to the GIC */
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qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
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qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
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object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
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object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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mpcore_priv_map_setup(s);
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}
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static void mpcore_priv_initfn(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj);
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memory_region_init(&s->container, OBJECT(s),
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"mpcore-priv-container", 0x2000);
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sysbus_init_mmio(sbd, &s->container);
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object_initialize(&s->scu, sizeof(s->scu), TYPE_ARM11_SCU);
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qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
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object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
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qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
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/* Request the legacy 11MPCore GIC behaviour: */
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qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);
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object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER);
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qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default());
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object_initialize(&s->wdtimer, sizeof(s->wdtimer), TYPE_ARM_MPTIMER);
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qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default());
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}
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#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
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#define REALVIEW_MPCORE_RIRQ(obj) \
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OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
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/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
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controllers. The output of these, plus some of the raw input lines
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are fed into a single SMP-aware interrupt controller on the CPU. */
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typedef struct {
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SysBusDevice parent_obj;
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SysBusDevice *priv;
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qemu_irq cpuic[32];
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qemu_irq rvic[4][64];
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uint32_t num_cpu;
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} mpcore_rirq_state;
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/* Map baseboard IRQs onto CPU IRQ lines. */
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static const int mpcore_irq_map[32] = {
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-1, -1, -1, -1, 1, 2, -1, -1,
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-1, -1, 6, -1, 4, 5, -1, -1,
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-1, 14, 15, 0, 7, 8, -1, -1,
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-1, -1, -1, -1, 9, 3, -1, -1,
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};
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static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
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{
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mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
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int i;
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for (i = 0; i < 4; i++) {
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qemu_set_irq(s->rvic[i][irq], level);
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}
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if (irq < 32) {
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irq = mpcore_irq_map[irq];
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if (irq >= 0) {
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qemu_set_irq(s->cpuic[irq], level);
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}
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}
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}
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static int realview_mpcore_init(SysBusDevice *sbd)
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{
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DeviceState *dev = DEVICE(sbd);
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mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
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DeviceState *gic;
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DeviceState *priv;
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int n;
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int i;
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priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV);
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qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
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qdev_init_nofail(priv);
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s->priv = SYS_BUS_DEVICE(priv);
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sysbus_pass_irq(sbd, s->priv);
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for (i = 0; i < 32; i++) {
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s->cpuic[i] = qdev_get_gpio_in(priv, i);
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}
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/* ??? IRQ routing is hardcoded to "normal" mode. */
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for (n = 0; n < 4; n++) {
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gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
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s->cpuic[10 + n]);
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for (i = 0; i < 64; i++) {
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s->rvic[n][i] = qdev_get_gpio_in(gic, i);
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}
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}
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qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
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sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0));
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return 0;
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}
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static Property mpcore_rirq_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = realview_mpcore_init;
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dc->props = mpcore_rirq_properties;
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}
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static const TypeInfo mpcore_rirq_info = {
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.name = TYPE_REALVIEW_MPCORE_RIRQ,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(mpcore_rirq_state),
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.class_init = mpcore_rirq_class_init,
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};
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static Property mpcore_priv_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
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/* The ARM11 MPCORE TRM says the on-chip controller may have
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* anything from 0 to 224 external interrupt IRQ lines (with another
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* 32 internal). We default to 32+32, which is the number provided by
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* the ARM11 MPCore test chip in the Realview Versatile Express
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* coretile. Other boards may differ and should set this property
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* appropriately. Some Linux kernels may not boot if the hardware
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* has more IRQ lines than the kernel expects.
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*/
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DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mpcore_priv_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = mpcore_priv_realize;
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dc->props = mpcore_priv_properties;
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}
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static const TypeInfo mpcore_priv_info = {
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.name = TYPE_ARM11MPCORE_PRIV,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARM11MPCorePriveState),
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.instance_init = mpcore_priv_initfn,
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.class_init = mpcore_priv_class_init,
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};
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static void arm11mpcore_register_types(void)
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{
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type_register_static(&mpcore_rirq_info);
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type_register_static(&mpcore_priv_info);
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}
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type_init(arm11mpcore_register_types)
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