ce908a2f6f
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (1st stage bootloader). For detailed instructions on how to create images for the Icicle Kit board, please check QEMU RISC-V WiKi page at: https://wiki.qemu.org/Documentation/Platforms/RISCV Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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.. | ||
boot.h | ||
boot_opensbi.h | ||
microchip_pfsoc.h | ||
numa.h | ||
opentitan.h | ||
riscv_hart.h | ||
riscv_htif.h | ||
sifive_clint.h | ||
sifive_cpu.h | ||
sifive_e.h | ||
sifive_e_prci.h | ||
sifive_gpio.h | ||
sifive_plic.h | ||
sifive_test.h | ||
sifive_u.h | ||
sifive_u_otp.h | ||
sifive_u_prci.h | ||
sifive_uart.h | ||
spike.h | ||
virt.h |