Simplify logic for hotplug notification, by tracking state of the logical interrupt condition. We then simply use this variable to make the interrupt decision, according to spec. API is made cleaner as we no longer force users to pass in old slot control value. Includes fixes by Isaku Yamahata. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
187 lines
5.3 KiB
C
187 lines
5.3 KiB
C
/*
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* ioh3420.c
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* Intel X58 north bridge IOH
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* PCI Express root port device id 3420
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "pci_ids.h"
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#include "msi.h"
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#include "pcie.h"
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#include "ioh3420.h"
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#define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */
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#define PCI_DEVICE_ID_IOH_REV 0x2
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#define IOH_EP_SSVID_OFFSET 0x40
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#define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL
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#define IOH_EP_SSVID_SSID 0
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#define IOH_EP_MSI_OFFSET 0x60
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#define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
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#define IOH_EP_MSI_NR_VECTOR 2
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#define IOH_EP_EXP_OFFSET 0x90
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#define IOH_EP_AER_OFFSET 0x100
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static void ioh3420_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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pci_bridge_write_config(d, address, val, len);
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msi_write_config(d, address, val, len);
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pcie_cap_slot_write_config(d, address, val, len);
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/* TODO: AER */
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}
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static void ioh3420_reset(DeviceState *qdev)
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{
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PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
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msi_reset(d);
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pcie_cap_root_reset(d);
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pcie_cap_deverr_reset(d);
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pcie_cap_slot_reset(d);
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pci_bridge_reset(qdev);
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pci_bridge_disable_base_limit(d);
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/* TODO: AER */
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}
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static int ioh3420_initfn(PCIDevice *d)
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{
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PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
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PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
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PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
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int rc;
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rc = pci_bridge_initfn(d);
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if (rc < 0) {
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return rc;
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}
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d->config[PCI_REVISION_ID] = PCI_DEVICE_ID_IOH_REV;
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pcie_port_init_reg(d);
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_IOH_EPORT);
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rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
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IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
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if (rc < 0) {
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return rc;
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}
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rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
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IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
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IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
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if (rc < 0) {
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return rc;
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}
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rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
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if (rc < 0) {
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return rc;
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}
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pcie_cap_deverr_init(d);
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pcie_cap_slot_init(d, s->slot);
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pcie_chassis_create(s->chassis);
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rc = pcie_chassis_add_slot(s);
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if (rc < 0) {
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return rc;
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}
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pcie_cap_root_init(d);
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/* TODO: AER */
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return 0;
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}
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static int ioh3420_exitfn(PCIDevice *d)
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{
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/* TODO: AER */
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msi_uninit(d);
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pcie_cap_exit(d);
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return pci_bridge_exitfn(d);
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}
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PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,
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const char *bus_name, pci_map_irq_fn map_irq,
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uint8_t port, uint8_t chassis, uint16_t slot)
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{
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PCIDevice *d;
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PCIBridge *br;
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DeviceState *qdev;
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d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420");
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if (!d) {
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return NULL;
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}
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br = DO_UPCAST(PCIBridge, dev, d);
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qdev = &br->dev.qdev;
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pci_bridge_map_irq(br, bus_name, map_irq);
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qdev_prop_set_uint8(qdev, "port", port);
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qdev_prop_set_uint8(qdev, "chassis", chassis);
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qdev_prop_set_uint16(qdev, "slot", slot);
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qdev_init_nofail(qdev);
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return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
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}
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static const VMStateDescription vmstate_ioh3420 = {
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.name = "ioh-3240-express-root-port",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = pcie_cap_slot_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
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/* TODO: AER */
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VMSTATE_END_OF_LIST()
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}
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};
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static PCIDeviceInfo ioh3420_info = {
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.qdev.name = "ioh3420",
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.qdev.desc = "Intel IOH device id 3420 PCIE Root Port",
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.qdev.size = sizeof(PCIESlot),
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.qdev.reset = ioh3420_reset,
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.qdev.vmsd = &vmstate_ioh3420,
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.is_express = 1,
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.is_bridge = 1,
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.config_write = ioh3420_write_config,
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.init = ioh3420_initfn,
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.exit = ioh3420_exitfn,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
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DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
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DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
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/* TODO: AER */
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void ioh3420_register(void)
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{
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pci_qdev_register(&ioh3420_info);
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}
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device_init(ioh3420_register);
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/*
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* Local variables:
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* c-indent-level: 4
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* c-basic-offset: 4
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* tab-width: 8
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* indent-tab-mode: nil
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* End:
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*/
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