git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@119 c046a42c-6fe2-441c-8c8c-71466251a162
555 lines
14 KiB
C
555 lines
14 KiB
C
/*
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* i386 emulator main execution loop
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec-i386.h"
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#include "disas.h"
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//#define DEBUG_EXEC
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#define DEBUG_FLUSH
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//#define DEBUG_SIGNAL
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/* main execution loop */
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/* maximum total translate dcode allocated */
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#define CODE_GEN_BUFFER_SIZE (2048 * 1024)
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//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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#define CODE_GEN_MAX_SIZE 65536
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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/* threshold to flush the translated code buffer */
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#define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)
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#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / 64)
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#define CODE_GEN_HASH_BITS 15
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#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
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typedef struct TranslationBlock {
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unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
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unsigned long cs_base; /* CS base for this block */
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unsigned int flags; /* flags defining in which context the code was generated */
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uint8_t *tc_ptr; /* pointer to the translated code */
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struct TranslationBlock *hash_next; /* next matching block */
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} TranslationBlock;
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TranslationBlock tbs[CODE_GEN_MAX_BLOCKS];
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TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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int nb_tbs;
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uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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uint8_t *code_gen_ptr;
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/* thread support */
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#ifdef __powerpc__
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ (
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"0: lwarx %0,0,%1 ;"
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" xor. %0,%3,%0;"
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" bne 1f;"
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" stwcx. %2,0,%1;"
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" bne- 0b;"
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"1: "
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: "=&r" (ret)
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: "r" (p), "r" (1), "r" (0)
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: "cr0", "memory");
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return ret;
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}
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#endif
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#ifdef __i386__
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static inline int testandset (int *p)
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{
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char ret;
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long int readval;
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__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
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: "=q" (ret), "=m" (*p), "=a" (readval)
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: "r" (1), "m" (*p), "a" (0)
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: "memory");
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return ret;
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}
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#endif
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#ifdef __s390__
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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" jl 0b"
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: "=&d" (ret)
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: "r" (1), "a" (p), "0" (*p)
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: "cc", "memory" );
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return ret;
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}
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#endif
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#ifdef __alpha__
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int testandset (int *p)
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{
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int ret;
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unsigned long one;
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__asm__ __volatile__ ("0: mov 1,%2\n"
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" ldl_l %0,%1\n"
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" stl_c %2,%1\n"
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" beq %2,1f\n"
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".subsection 2\n"
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"1: br 0b\n"
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".previous"
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: "=r" (ret), "=m" (*p), "=r" (one)
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: "m" (*p));
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return ret;
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}
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#endif
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#ifdef __sparc__
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__("ldstub [%1], %0"
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: "=r" (ret)
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: "r" (p)
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: "memory");
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return (ret ? 1 : 0);
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}
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#endif
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int global_cpu_lock = 0;
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void cpu_lock(void)
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{
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while (testandset(&global_cpu_lock));
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}
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void cpu_unlock(void)
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{
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global_cpu_lock = 0;
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}
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/* exception support */
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/* NOTE: not static to force relocation generation by GCC */
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void raise_exception(int exception_index)
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{
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/* NOTE: the register at this point must be saved by hand because
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longjmp restore them */
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#ifdef reg_EAX
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env->regs[R_EAX] = EAX;
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#endif
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#ifdef reg_ECX
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env->regs[R_ECX] = ECX;
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#endif
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#ifdef reg_EDX
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env->regs[R_EDX] = EDX;
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#endif
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#ifdef reg_EBX
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env->regs[R_EBX] = EBX;
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#endif
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#ifdef reg_ESP
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env->regs[R_ESP] = ESP;
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#endif
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#ifdef reg_EBP
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env->regs[R_EBP] = EBP;
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#endif
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#ifdef reg_ESI
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env->regs[R_ESI] = ESI;
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#endif
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#ifdef reg_EDI
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env->regs[R_EDI] = EDI;
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#endif
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env->exception_index = exception_index;
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longjmp(env->jmp_env, 1);
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}
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#if defined(DEBUG_EXEC)
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static const char *cc_op_str[] = {
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"DYNAMIC",
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"EFLAGS",
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"MUL",
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"ADDB",
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"ADDW",
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"ADDL",
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"ADCB",
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"ADCW",
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"ADCL",
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"SUBB",
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"SUBW",
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"SUBL",
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"SBBB",
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"SBBW",
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"SBBL",
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"LOGICB",
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"LOGICW",
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"LOGICL",
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"INCB",
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"INCW",
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"INCL",
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"DECB",
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"DECW",
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"DECL",
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"SHLB",
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"SHLW",
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"SHLL",
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"SARB",
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"SARW",
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"SARL",
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};
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static void cpu_x86_dump_state(FILE *f)
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{
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int eflags;
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eflags = cc_table[CC_OP].compute_all();
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eflags |= (DF & DF_MASK);
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fprintf(f,
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"EAX=%08x EBX=%08X ECX=%08x EDX=%08x\n"
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"ESI=%08x EDI=%08X EBP=%08x ESP=%08x\n"
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"CCS=%08x CCD=%08x CCO=%-8s EFL=%c%c%c%c%c%c%c\n"
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"EIP=%08x\n",
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env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX],
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env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP],
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env->cc_src, env->cc_dst, cc_op_str[env->cc_op],
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eflags & DF_MASK ? 'D' : '-',
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eflags & CC_O ? 'O' : '-',
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eflags & CC_S ? 'S' : '-',
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eflags & CC_Z ? 'Z' : '-',
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eflags & CC_A ? 'A' : '-',
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eflags & CC_P ? 'P' : '-',
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eflags & CC_C ? 'C' : '-',
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env->eip);
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#if 1
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fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
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(double)ST0, (double)ST1, (double)ST(2), (double)ST(3));
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#endif
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}
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#endif
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void cpu_x86_tblocks_init(void)
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{
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if (!code_gen_ptr) {
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code_gen_ptr = code_gen_buffer;
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}
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}
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/* flush all the translation blocks */
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static void tb_flush(void)
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{
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int i;
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#ifdef DEBUG_FLUSH
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printf("gemu: flush code_size=%d nb_tbs=%d avg_tb_size=%d\n",
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code_gen_ptr - code_gen_buffer,
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nb_tbs,
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(code_gen_ptr - code_gen_buffer) / nb_tbs);
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#endif
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nb_tbs = 0;
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for(i = 0;i < CODE_GEN_HASH_SIZE; i++)
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tb_hash[i] = NULL;
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code_gen_ptr = code_gen_buffer;
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/* XXX: flush processor icache at this point */
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}
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/* find a translation block in the translation cache. If not found,
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return NULL and the pointer to the last element of the list in pptb */
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static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
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unsigned long pc,
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unsigned long cs_base,
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unsigned int flags)
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{
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TranslationBlock **ptb, *tb;
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unsigned int h;
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h = pc & (CODE_GEN_HASH_SIZE - 1);
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ptb = &tb_hash[h];
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for(;;) {
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tb = *ptb;
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if (!tb)
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break;
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if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
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return tb;
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ptb = &tb->hash_next;
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}
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*pptb = ptb;
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return NULL;
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}
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/* allocate a new translation block. flush the translation buffer if
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too many translation blocks or too much generated code */
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static inline TranslationBlock *tb_alloc(void)
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{
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TranslationBlock *tb;
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if (nb_tbs >= CODE_GEN_MAX_BLOCKS ||
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(code_gen_ptr - code_gen_buffer) >= CODE_GEN_BUFFER_MAX_SIZE)
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tb_flush();
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tb = &tbs[nb_tbs++];
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return tb;
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}
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int cpu_x86_exec(CPUX86State *env1)
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{
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int saved_T0, saved_T1, saved_A0;
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CPUX86State *saved_env;
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#ifdef reg_EAX
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int saved_EAX;
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#endif
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#ifdef reg_ECX
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int saved_ECX;
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#endif
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#ifdef reg_EDX
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int saved_EDX;
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#endif
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#ifdef reg_EBX
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int saved_EBX;
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#endif
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#ifdef reg_ESP
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int saved_ESP;
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#endif
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#ifdef reg_EBP
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int saved_EBP;
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#endif
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#ifdef reg_ESI
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int saved_ESI;
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#endif
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#ifdef reg_EDI
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int saved_EDI;
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#endif
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int code_gen_size, ret;
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void (*gen_func)(void);
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TranslationBlock *tb, **ptb;
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uint8_t *tc_ptr, *cs_base, *pc;
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unsigned int flags;
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/* first we save global registers */
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saved_T0 = T0;
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saved_T1 = T1;
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saved_A0 = A0;
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saved_env = env;
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env = env1;
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#ifdef reg_EAX
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saved_EAX = EAX;
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EAX = env->regs[R_EAX];
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#endif
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#ifdef reg_ECX
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saved_ECX = ECX;
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ECX = env->regs[R_ECX];
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#endif
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#ifdef reg_EDX
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saved_EDX = EDX;
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EDX = env->regs[R_EDX];
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#endif
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#ifdef reg_EBX
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saved_EBX = EBX;
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EBX = env->regs[R_EBX];
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#endif
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#ifdef reg_ESP
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saved_ESP = ESP;
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ESP = env->regs[R_ESP];
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#endif
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#ifdef reg_EBP
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saved_EBP = EBP;
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EBP = env->regs[R_EBP];
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#endif
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#ifdef reg_ESI
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saved_ESI = ESI;
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ESI = env->regs[R_ESI];
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#endif
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#ifdef reg_EDI
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saved_EDI = EDI;
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EDI = env->regs[R_EDI];
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#endif
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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DF = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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env->interrupt_request = 0;
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/* prepare setjmp context for exception handling */
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if (setjmp(env->jmp_env) == 0) {
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for(;;) {
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if (env->interrupt_request) {
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raise_exception(EXCP_INTERRUPT);
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}
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#ifdef DEBUG_EXEC
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if (loglevel) {
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cpu_x86_dump_state(logfile);
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}
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#endif
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/* we compute the CPU state. We assume it will not
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change during the whole generated block. */
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flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
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flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
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flags |= (((unsigned long)env->seg_cache[R_DS].base |
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(unsigned long)env->seg_cache[R_ES].base |
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(unsigned long)env->seg_cache[R_SS].base) != 0) <<
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GEN_FLAG_ADDSEG_SHIFT;
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flags |= (env->eflags & VM_MASK) >> (17 - GEN_FLAG_VM_SHIFT);
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cs_base = env->seg_cache[R_CS].base;
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pc = cs_base + env->eip;
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
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flags);
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if (!tb) {
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/* if no translated code available, then translate it now */
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/* XXX: very inefficient: we lock all the cpus when
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generating code */
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cpu_lock();
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tc_ptr = code_gen_ptr;
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ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE,
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&code_gen_size, pc, cs_base, flags);
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/* if invalid instruction, signal it */
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if (ret != 0) {
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cpu_unlock();
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raise_exception(EXCP06_ILLOP);
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}
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tb = tb_alloc();
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*ptb = tb;
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tb->pc = (unsigned long)pc;
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tb->cs_base = (unsigned long)cs_base;
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tb->flags = flags;
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tb->tc_ptr = tc_ptr;
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tb->hash_next = NULL;
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
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cpu_unlock();
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}
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if (loglevel) {
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fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
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(long)tb->tc_ptr, (long)tb->pc,
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lookup_symbol((void *)tb->pc));
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fflush(logfile);
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}
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/* execute the generated code */
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tc_ptr = tb->tc_ptr;
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gen_func = (void *)tc_ptr;
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gen_func();
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}
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}
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ret = env->exception_index;
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/* restore flags in standard format */
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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/* restore global registers */
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#ifdef reg_EAX
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EAX = saved_EAX;
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#endif
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#ifdef reg_ECX
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ECX = saved_ECX;
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#endif
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#ifdef reg_EDX
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EDX = saved_EDX;
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#endif
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#ifdef reg_EBX
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EBX = saved_EBX;
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#endif
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#ifdef reg_ESP
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ESP = saved_ESP;
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#endif
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#ifdef reg_EBP
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EBP = saved_EBP;
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#endif
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#ifdef reg_ESI
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ESI = saved_ESI;
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#endif
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#ifdef reg_EDI
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EDI = saved_EDI;
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#endif
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T0 = saved_T0;
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T1 = saved_T1;
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A0 = saved_A0;
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env = saved_env;
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return ret;
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}
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void cpu_x86_interrupt(CPUX86State *s)
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{
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s->interrupt_request = 1;
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}
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void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
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{
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CPUX86State *saved_env;
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saved_env = env;
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env = s;
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load_seg(seg_reg, selector);
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env = saved_env;
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}
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#include <signal.h>
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#include <sys/ucontext.h>
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static inline int handle_cpu_signal(unsigned long pc,
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sigset_t *old_set)
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{
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#ifdef DEBUG_SIGNAL
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printf("gemu: SIGSEGV pc=0x%08lx oldset=0x%08lx\n",
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pc, *(unsigned long *)old_set);
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#endif
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if (pc >= (unsigned long)code_gen_buffer &&
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pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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/* we restore the process signal mask as the sigreturn should
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do it */
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sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
/* XXX: need to compute virtual pc position by retranslating
|
|
code. The rest of the CPU state should be correct. */
|
|
raise_exception(EXCP0D_GPF);
|
|
/* never comes here */
|
|
return 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
#if defined(__i386__)
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
sigset_t *pold_set;
|
|
|
|
#ifndef REG_EIP
|
|
/* for glibc 2.1 */
|
|
#define REG_EIP EIP
|
|
#endif
|
|
pc = uc->uc_mcontext.gregs[REG_EIP];
|
|
pold_set = &uc->uc_sigmask;
|
|
return handle_cpu_signal(pc, pold_set);
|
|
#else
|
|
#warning No CPU specific signal handler: cannot handle target SIGSEGV events
|
|
return 0;
|
|
#endif
|
|
}
|