When all we do with an Error we receive into a local variable is propagating to somewhere else, we can just as well receive it there right away. Convert if (!foo(..., &err)) { ... error_propagate(errp, err); ... return ... } to if (!foo(..., errp)) { ... ... return ... } where nothing else needs @err. Coccinelle script: @rule1 forall@ identifier fun, err, errp, lbl; expression list args, args2; binary operator op; constant c1, c2; symbol false; @@ if ( ( - fun(args, &err, args2) + fun(args, errp, args2) | - !fun(args, &err, args2) + !fun(args, errp, args2) | - fun(args, &err, args2) op c1 + fun(args, errp, args2) op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; ) } @rule2 forall@ identifier fun, err, errp, lbl; expression list args, args2; expression var; binary operator op; constant c1, c2; symbol false; @@ - var = fun(args, &err, args2); + var = fun(args, errp, args2); ... when != err if ( ( var | !var | var op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; | return var; ) } @depends on rule1 || rule2@ identifier err; @@ - Error *err = NULL; ... when != err Not exactly elegant, I'm afraid. The "when != lbl:" is necessary to avoid transforming if (fun(args, &err)) { goto out } ... out: error_propagate(errp, err); even though other paths to label out still need the error_propagate(). For an actual example, see sclp_realize(). Without the "when strict", Coccinelle transforms vfio_msix_setup(), incorrectly. I don't know what exactly "when strict" does, only that it helps here. The match of return is narrower than what I want, but I can't figure out how to express "return where the operand doesn't use @err". For an example where it's too narrow, see vfio_intx_enable(). Silently fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Converted manually. Line breaks tidied up manually. One nested declaration of @local_err deleted manually. Preexisting unwanted blank line dropped in hw/riscv/sifive_e.c. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20200707160613.848843-35-armbru@redhat.com>
196 lines
6.3 KiB
C
196 lines
6.3 KiB
C
/*
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* Coherent Processing System emulation.
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/mips/cps.h"
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#include "hw/mips/mips.h"
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#include "hw/qdev-properties.h"
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#include "hw/mips/cpudevs.h"
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#include "sysemu/kvm.h"
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#include "sysemu/reset.h"
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qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
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{
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assert(pin_number < s->num_irq);
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return s->gic.irq_state[pin_number].irq;
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}
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static void mips_cps_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MIPSCPSState *s = MIPS_CPS(obj);
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/*
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* Cover entire address space as there do not seem to be any
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* constraints for the base address of CPC and GIC.
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*/
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memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
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sysbus_init_mmio(sbd, &s->container);
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}
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static void main_cpu_reset(void *opaque)
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{
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MIPSCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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cpu_reset(cs);
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/* All VPs are halted on reset. Leave powering up to CPC. */
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cs->halted = 1;
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}
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static bool cpu_mips_itu_supported(CPUMIPSState *env)
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{
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bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
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(env->CP0_Config3 & (1 << CP0C3_MT));
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return is_mt && !kvm_enabled();
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}
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static void mips_cps_realize(DeviceState *dev, Error **errp)
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{
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MIPSCPSState *s = MIPS_CPS(dev);
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CPUMIPSState *env;
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MIPSCPU *cpu;
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int i;
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target_ulong gcr_base;
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bool itu_present = false;
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bool saar_present = false;
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for (i = 0; i < s->num_vp; i++) {
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cpu = MIPS_CPU(cpu_create(s->cpu_type));
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/* Init internal devices */
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cpu_mips_irq_init_cpu(cpu);
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cpu_mips_clock_init(cpu);
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env = &cpu->env;
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if (cpu_mips_itu_supported(env)) {
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itu_present = true;
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/* Attach ITC Tag to the VP */
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env->itc_tag = mips_itu_get_tag_region(&s->itu);
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env->itu = &s->itu;
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}
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qemu_register_reset(main_cpu_reset, cpu);
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}
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cpu = MIPS_CPU(first_cpu);
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env = &cpu->env;
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saar_present = (bool)env->saarp;
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/* Inter-Thread Communication Unit */
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if (itu_present) {
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object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
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object_property_set_int(OBJECT(&s->itu), "num-fifo", 16,
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&error_abort);
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object_property_set_int(OBJECT(&s->itu), "num-semaphores", 16,
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&error_abort);
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object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present,
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&error_abort);
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if (saar_present) {
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s->itu.saar = &env->CP0_SAAR;
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}
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) {
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
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}
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/* Cluster Power Controller */
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object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC);
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object_property_set_int(OBJECT(&s->cpc), "num-vp", s->num_vp,
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&error_abort);
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object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1,
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) {
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
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/* Global Interrupt Controller */
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object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC);
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object_property_set_int(OBJECT(&s->gic), "num-vp", s->num_vp,
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&error_abort);
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object_property_set_int(OBJECT(&s->gic), "num-irq", 128,
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
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/* Global Configuration Registers */
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gcr_base = env->CP0_CMGCRBase << 4;
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object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
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object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp,
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&error_abort);
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object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800,
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&error_abort);
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object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base,
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&error_abort);
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object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr),
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&error_abort);
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object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
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return;
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}
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memory_region_add_subregion(&s->container, gcr_base,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
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}
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static Property mips_cps_properties[] = {
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DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
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DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
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DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
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DEFINE_PROP_END_OF_LIST()
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};
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static void mips_cps_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = mips_cps_realize;
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device_class_set_props(dc, mips_cps_properties);
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}
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static const TypeInfo mips_cps_info = {
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.name = TYPE_MIPS_CPS,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MIPSCPSState),
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.instance_init = mips_cps_init,
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.class_init = mips_cps_class_init,
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};
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static void mips_cps_register_types(void)
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{
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type_register_static(&mips_cps_info);
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}
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type_init(mips_cps_register_types)
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