qemu-patch-raspberry4/target/riscv
Michael Clark d1fd31f822 RISC-V: Fix riscv_isa_string memory size bug
This version uses a constant size memory buffer sized for
the maximum possible ISA string length. It also uses g_new
instead of g_new0, uses more efficient logic to append
extensions and adds manual zero termination of the string.

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMM: Use qemu_tolower() rather than tolower()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-20 11:45:55 +00:00
..
cpu.c RISC-V: Fix riscv_isa_string memory size bug 2018-03-20 11:45:55 +00:00
cpu.h
cpu_bits.h
cpu_user.h RISC-V Linux User Emulation 2018-03-07 08:30:28 +13:00
fpu_helper.c RISC-V FPU Support 2018-03-07 08:30:28 +13:00
gdbstub.c RISC-V GDB Stub 2018-03-07 08:30:28 +13:00
helper.c RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
helper.h RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
Makefile.objs RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
op_helper.c RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
pmp.c RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
pmp.h RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
translate.c RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00