git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1023 c046a42c-6fe2-441c-8c8c-71466251a162
234 lines
7.5 KiB
C
234 lines
7.5 KiB
C
/*
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* QEMU PPC CHRP/PMAC hardware System Emulator
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#define BIOS_FILENAME "ppc_rom.bin"
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#define NVRAM_SIZE 0x2000
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#define KERNEL_LOAD_ADDR 0x01000000
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#define INITRD_LOAD_ADDR 0x01800000
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/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
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NVRAM (not implemented). */
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static int dbdma_mem_index;
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static int cuda_mem_index;
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static int ide0_mem_index;
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static int ide1_mem_index;
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static int openpic_mem_index;
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/* DBDMA: currently no op - should suffice right now */
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static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
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}
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static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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}
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static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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}
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static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
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{
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printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
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return 0;
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}
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static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static CPUWriteMemoryFunc *dbdma_write[] = {
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&dbdma_writeb,
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&dbdma_writew,
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&dbdma_writel,
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};
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static CPUReadMemoryFunc *dbdma_read[] = {
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&dbdma_readb,
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&dbdma_readw,
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&dbdma_readl,
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};
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static void macio_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
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cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
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cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
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cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
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cpu_register_physical_memory(addr + 0x40000, 0x40000, openpic_mem_index);
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}
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static void macio_init(PCIBus *bus)
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{
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PCIDevice *d;
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d = pci_register_device(bus, "macio", sizeof(PCIDevice),
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-1, NULL, NULL);
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/* Note: this code is strongly inspirated from the corresponding code
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in PearPC */
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d->config[0x00] = 0x6b; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x22;
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d->config[0x03] = 0x00;
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d->config[0x0a] = 0x00; // class_sub = pci2pci
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d->config[0x0b] = 0xff; // class_base = bridge
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d->config[0x0e] = 0x00; // header_type
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d->config[0x3d] = 0x01; // interrupt on pin 1
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dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
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pci_register_io_region(d, 0, 0x80000,
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PCI_ADDRESS_SPACE_MEM, macio_map);
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}
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/* PowerPC PREP hardware initialisation */
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void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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{
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char buf[1024];
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openpic_t *openpic;
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m48t59_t *nvram;
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int PPC_io_memory;
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int ret, linux_boot, i;
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unsigned long bios_offset;
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uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
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PCIBus *pci_bus;
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linux_boot = (kernel_filename != NULL);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* allocate and load BIOS */
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bios_offset = ram_size + vga_ram_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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ret = load_image(buf, phys_ram_base + bios_offset);
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if (ret != BIOS_SIZE) {
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fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
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exit(1);
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}
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cpu_register_physical_memory((uint32_t)(-BIOS_SIZE),
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BIOS_SIZE, bios_offset | IO_MEM_ROM);
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cpu_single_env->nip = 0xfffffffc;
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if (linux_boot) {
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kernel_base = KERNEL_LOAD_ADDR;
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/* now we can load the kernel */
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR;
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initrd_size = load_image(initrd_filename,
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phys_ram_base + initrd_base);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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} else {
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initrd_base = 0;
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initrd_size = 0;
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}
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boot_device = 'm';
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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}
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/* Register CPU as a 74x/75x */
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cpu_ppc_register(cpu_single_env, 0x00080000);
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
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isa_mem_base = 0x80000000;
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pci_bus = pci_pmac_init();
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/* Register 8 MB of ISA IO space */
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PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
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cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory);
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/* init basic PC hardware */
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vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size);
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openpic = openpic_init(NULL, &openpic_mem_index, 1);
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pci_pmac_set_openpic(pci_bus, openpic);
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/* XXX: suppress that */
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pic_init();
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, 4, serial_hd);
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for(i = 0; i < nb_nics; i++) {
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pci_ne2000_init(pci_bus, &nd_table[i]);
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}
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ide0_mem_index = pmac_ide_init(&bs_table[0], openpic, 0x13);
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ide1_mem_index = pmac_ide_init(&bs_table[2], openpic, 0x13);
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/* cuda also initialize ADB */
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cuda_mem_index = cuda_init(openpic, 0x19);
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adb_kbd_init(&adb_bus);
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adb_mouse_init(&adb_bus);
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macio_init(pci_bus);
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nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
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if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
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graphic_depth = 15;
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PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "CHRP", ram_size, boot_device,
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kernel_base, kernel_size,
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kernel_cmdline,
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initrd_base, initrd_size,
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/* XXX: need an option to load a NVRAM image */
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0,
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graphic_width, graphic_height, graphic_depth);
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/* No PCI init: the BIOS will do it */
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}
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