Update our copy of libvixl to upstream's 1.7 release.
This includes upstream's fix for the issue we had a local
patch for in commit 94cc44a9e
.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1422274779-13359-2-git-send-email-peter.maydell@linaro.org
385 lines
12 KiB
C++
385 lines
12 KiB
C++
// Copyright 2013, ARM Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef VIXL_A64_INSTRUCTIONS_A64_H_
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#define VIXL_A64_INSTRUCTIONS_A64_H_
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#include "globals.h"
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#include "utils.h"
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#include "a64/constants-a64.h"
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namespace vixl {
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// ISA constants. --------------------------------------------------------------
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typedef uint32_t Instr;
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const unsigned kInstructionSize = 4;
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const unsigned kInstructionSizeLog2 = 2;
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const unsigned kLiteralEntrySize = 4;
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const unsigned kLiteralEntrySizeLog2 = 2;
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const unsigned kMaxLoadLiteralRange = 1 * MBytes;
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// This is the nominal page size (as used by the adrp instruction); the actual
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// size of the memory pages allocated by the kernel is likely to differ.
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const unsigned kPageSize = 4 * KBytes;
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const unsigned kPageSizeLog2 = 12;
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const unsigned kWRegSize = 32;
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const unsigned kWRegSizeLog2 = 5;
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const unsigned kWRegSizeInBytes = kWRegSize / 8;
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const unsigned kWRegSizeInBytesLog2 = kWRegSizeLog2 - 3;
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const unsigned kXRegSize = 64;
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const unsigned kXRegSizeLog2 = 6;
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const unsigned kXRegSizeInBytes = kXRegSize / 8;
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const unsigned kXRegSizeInBytesLog2 = kXRegSizeLog2 - 3;
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const unsigned kSRegSize = 32;
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const unsigned kSRegSizeLog2 = 5;
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const unsigned kSRegSizeInBytes = kSRegSize / 8;
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const unsigned kSRegSizeInBytesLog2 = kSRegSizeLog2 - 3;
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const unsigned kDRegSize = 64;
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const unsigned kDRegSizeLog2 = 6;
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const unsigned kDRegSizeInBytes = kDRegSize / 8;
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const unsigned kDRegSizeInBytesLog2 = kDRegSizeLog2 - 3;
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const uint64_t kWRegMask = UINT64_C(0xffffffff);
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const uint64_t kXRegMask = UINT64_C(0xffffffffffffffff);
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const uint64_t kSRegMask = UINT64_C(0xffffffff);
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const uint64_t kDRegMask = UINT64_C(0xffffffffffffffff);
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const uint64_t kSSignMask = UINT64_C(0x80000000);
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const uint64_t kDSignMask = UINT64_C(0x8000000000000000);
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const uint64_t kWSignMask = UINT64_C(0x80000000);
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const uint64_t kXSignMask = UINT64_C(0x8000000000000000);
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const uint64_t kByteMask = UINT64_C(0xff);
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const uint64_t kHalfWordMask = UINT64_C(0xffff);
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const uint64_t kWordMask = UINT64_C(0xffffffff);
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const uint64_t kXMaxUInt = UINT64_C(0xffffffffffffffff);
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const uint64_t kWMaxUInt = UINT64_C(0xffffffff);
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const int64_t kXMaxInt = INT64_C(0x7fffffffffffffff);
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const int64_t kXMinInt = INT64_C(0x8000000000000000);
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const int32_t kWMaxInt = INT32_C(0x7fffffff);
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const int32_t kWMinInt = INT32_C(0x80000000);
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const unsigned kLinkRegCode = 30;
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const unsigned kZeroRegCode = 31;
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const unsigned kSPRegInternalCode = 63;
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const unsigned kRegCodeMask = 0x1f;
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const unsigned kAddressTagOffset = 56;
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const unsigned kAddressTagWidth = 8;
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const uint64_t kAddressTagMask =
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((UINT64_C(1) << kAddressTagWidth) - 1) << kAddressTagOffset;
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VIXL_STATIC_ASSERT(kAddressTagMask == UINT64_C(0xff00000000000000));
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// AArch64 floating-point specifics. These match IEEE-754.
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const unsigned kDoubleMantissaBits = 52;
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const unsigned kDoubleExponentBits = 11;
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const unsigned kFloatMantissaBits = 23;
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const unsigned kFloatExponentBits = 8;
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// Floating-point infinity values.
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extern const float kFP32PositiveInfinity;
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extern const float kFP32NegativeInfinity;
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extern const double kFP64PositiveInfinity;
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extern const double kFP64NegativeInfinity;
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// The default NaN values (for FPCR.DN=1).
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extern const double kFP64DefaultNaN;
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extern const float kFP32DefaultNaN;
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enum LSDataSize {
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LSByte = 0,
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LSHalfword = 1,
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LSWord = 2,
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LSDoubleWord = 3
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};
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LSDataSize CalcLSPairDataSize(LoadStorePairOp op);
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enum ImmBranchType {
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UnknownBranchType = 0,
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CondBranchType = 1,
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UncondBranchType = 2,
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CompareBranchType = 3,
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TestBranchType = 4
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};
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enum AddrMode {
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Offset,
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PreIndex,
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PostIndex
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};
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enum FPRounding {
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// The first four values are encodable directly by FPCR<RMode>.
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FPTieEven = 0x0,
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FPPositiveInfinity = 0x1,
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FPNegativeInfinity = 0x2,
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FPZero = 0x3,
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// The final rounding mode is only available when explicitly specified by the
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// instruction (such as with fcvta). It cannot be set in FPCR.
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FPTieAway
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};
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enum Reg31Mode {
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Reg31IsStackPointer,
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Reg31IsZeroRegister
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};
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// Instructions. ---------------------------------------------------------------
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class Instruction {
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public:
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Instr InstructionBits() const {
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return *(reinterpret_cast<const Instr*>(this));
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}
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void SetInstructionBits(Instr new_instr) {
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*(reinterpret_cast<Instr*>(this)) = new_instr;
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}
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int Bit(int pos) const {
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return (InstructionBits() >> pos) & 1;
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}
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uint32_t Bits(int msb, int lsb) const {
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return unsigned_bitextract_32(msb, lsb, InstructionBits());
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}
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int32_t SignedBits(int msb, int lsb) const {
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int32_t bits = *(reinterpret_cast<const int32_t*>(this));
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return signed_bitextract_32(msb, lsb, bits);
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}
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Instr Mask(uint32_t mask) const {
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return InstructionBits() & mask;
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}
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#define DEFINE_GETTER(Name, HighBit, LowBit, Func) \
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int64_t Name() const { return Func(HighBit, LowBit); }
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INSTRUCTION_FIELDS_LIST(DEFINE_GETTER)
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#undef DEFINE_GETTER
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// ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST),
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// formed from ImmPCRelLo and ImmPCRelHi.
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int ImmPCRel() const {
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int const offset = ((ImmPCRelHi() << ImmPCRelLo_width) | ImmPCRelLo());
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int const width = ImmPCRelLo_width + ImmPCRelHi_width;
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return signed_bitextract_32(width-1, 0, offset);
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}
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uint64_t ImmLogical() const;
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float ImmFP32() const;
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double ImmFP64() const;
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LSDataSize SizeLSPair() const {
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return CalcLSPairDataSize(
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static_cast<LoadStorePairOp>(Mask(LoadStorePairMask)));
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}
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// Helpers.
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bool IsCondBranchImm() const {
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return Mask(ConditionalBranchFMask) == ConditionalBranchFixed;
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}
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bool IsUncondBranchImm() const {
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return Mask(UnconditionalBranchFMask) == UnconditionalBranchFixed;
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}
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bool IsCompareBranch() const {
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return Mask(CompareBranchFMask) == CompareBranchFixed;
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}
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bool IsTestBranch() const {
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return Mask(TestBranchFMask) == TestBranchFixed;
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}
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bool IsPCRelAddressing() const {
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return Mask(PCRelAddressingFMask) == PCRelAddressingFixed;
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}
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bool IsLogicalImmediate() const {
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return Mask(LogicalImmediateFMask) == LogicalImmediateFixed;
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}
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bool IsAddSubImmediate() const {
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return Mask(AddSubImmediateFMask) == AddSubImmediateFixed;
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}
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bool IsAddSubExtended() const {
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return Mask(AddSubExtendedFMask) == AddSubExtendedFixed;
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}
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bool IsLoadOrStore() const {
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return Mask(LoadStoreAnyFMask) == LoadStoreAnyFixed;
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}
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bool IsLoad() const;
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bool IsStore() const;
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bool IsLoadLiteral() const {
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// This includes PRFM_lit.
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return Mask(LoadLiteralFMask) == LoadLiteralFixed;
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}
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bool IsMovn() const {
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return (Mask(MoveWideImmediateMask) == MOVN_x) ||
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(Mask(MoveWideImmediateMask) == MOVN_w);
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}
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// Indicate whether Rd can be the stack pointer or the zero register. This
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// does not check that the instruction actually has an Rd field.
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Reg31Mode RdMode() const {
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// The following instructions use sp or wsp as Rd:
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// Add/sub (immediate) when not setting the flags.
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// Add/sub (extended) when not setting the flags.
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// Logical (immediate) when not setting the flags.
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// Otherwise, r31 is the zero register.
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if (IsAddSubImmediate() || IsAddSubExtended()) {
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if (Mask(AddSubSetFlagsBit)) {
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return Reg31IsZeroRegister;
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} else {
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return Reg31IsStackPointer;
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}
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}
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if (IsLogicalImmediate()) {
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// Of the logical (immediate) instructions, only ANDS (and its aliases)
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// can set the flags. The others can all write into sp.
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// Note that some logical operations are not available to
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// immediate-operand instructions, so we have to combine two masks here.
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if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) {
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return Reg31IsZeroRegister;
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} else {
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return Reg31IsStackPointer;
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}
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}
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return Reg31IsZeroRegister;
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}
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// Indicate whether Rn can be the stack pointer or the zero register. This
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// does not check that the instruction actually has an Rn field.
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Reg31Mode RnMode() const {
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// The following instructions use sp or wsp as Rn:
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// All loads and stores.
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// Add/sub (immediate).
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// Add/sub (extended).
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// Otherwise, r31 is the zero register.
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if (IsLoadOrStore() || IsAddSubImmediate() || IsAddSubExtended()) {
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return Reg31IsStackPointer;
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}
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return Reg31IsZeroRegister;
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}
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ImmBranchType BranchType() const {
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if (IsCondBranchImm()) {
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return CondBranchType;
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} else if (IsUncondBranchImm()) {
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return UncondBranchType;
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} else if (IsCompareBranch()) {
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return CompareBranchType;
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} else if (IsTestBranch()) {
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return TestBranchType;
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} else {
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return UnknownBranchType;
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}
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}
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// Find the target of this instruction. 'this' may be a branch or a
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// PC-relative addressing instruction.
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const Instruction* ImmPCOffsetTarget() const;
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// Patch a PC-relative offset to refer to 'target'. 'this' may be a branch or
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// a PC-relative addressing instruction.
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void SetImmPCOffsetTarget(const Instruction* target);
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// Patch a literal load instruction to load from 'source'.
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void SetImmLLiteral(const Instruction* source);
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// Calculate the address of a literal referred to by a load-literal
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// instruction, and return it as the specified type.
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//
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// The literal itself is safely mutable only if the backing buffer is safely
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// mutable.
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template <typename T>
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T LiteralAddress() const {
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uint64_t base_raw = reinterpret_cast<uintptr_t>(this);
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ptrdiff_t offset = ImmLLiteral() << kLiteralEntrySizeLog2;
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uint64_t address_raw = base_raw + offset;
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// Cast the address using a C-style cast. A reinterpret_cast would be
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// appropriate, but it can't cast one integral type to another.
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T address = (T)(address_raw);
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// Assert that the address can be represented by the specified type.
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VIXL_ASSERT((uint64_t)(address) == address_raw);
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return address;
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}
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uint32_t Literal32() const {
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uint32_t literal;
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memcpy(&literal, LiteralAddress<const void*>(), sizeof(literal));
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return literal;
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}
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uint64_t Literal64() const {
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uint64_t literal;
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memcpy(&literal, LiteralAddress<const void*>(), sizeof(literal));
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return literal;
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}
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float LiteralFP32() const {
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return rawbits_to_float(Literal32());
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}
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double LiteralFP64() const {
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return rawbits_to_double(Literal64());
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}
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const Instruction* NextInstruction() const {
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return this + kInstructionSize;
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}
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const Instruction* InstructionAtOffset(int64_t offset) const {
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VIXL_ASSERT(IsWordAligned(this + offset));
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return this + offset;
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}
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template<typename T> static Instruction* Cast(T src) {
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return reinterpret_cast<Instruction*>(src);
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}
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template<typename T> static const Instruction* CastConst(T src) {
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return reinterpret_cast<const Instruction*>(src);
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}
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private:
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int ImmBranch() const;
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void SetPCRelImmTarget(const Instruction* target);
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void SetBranchImmTarget(const Instruction* target);
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};
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} // namespace vixl
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#endif // VIXL_A64_INSTRUCTIONS_A64_H_
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