There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023122801.19514-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
194 lines
5.3 KiB
C
194 lines
5.3 KiB
C
/*
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* x86 memory access helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "qemu/int128.h"
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#include "qemu/atomic128.h"
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#include "tcg/tcg.h"
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void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0)
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{
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uintptr_t ra = GETPC();
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uint64_t oldv, cmpv, newv;
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int eflags;
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eflags = cpu_cc_compute_all(env, CC_OP);
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cmpv = deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]);
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newv = deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]);
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oldv = cpu_ldq_data_ra(env, a0, ra);
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newv = (cmpv == oldv ? newv : oldv);
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/* always do the store */
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cpu_stq_data_ra(env, a0, newv, ra);
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if (oldv == cmpv) {
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eflags |= CC_Z;
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} else {
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env->regs[R_EAX] = (uint32_t)oldv;
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env->regs[R_EDX] = (uint32_t)(oldv >> 32);
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eflags &= ~CC_Z;
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}
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CC_SRC = eflags;
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}
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void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
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{
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#ifdef CONFIG_ATOMIC64
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uint64_t oldv, cmpv, newv;
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int eflags;
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eflags = cpu_cc_compute_all(env, CC_OP);
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cmpv = deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]);
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newv = deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]);
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#ifdef CONFIG_USER_ONLY
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{
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uint64_t *haddr = g2h(a0);
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cmpv = cpu_to_le64(cmpv);
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newv = cpu_to_le64(newv);
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oldv = qatomic_cmpxchg__nocheck(haddr, cmpv, newv);
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oldv = le64_to_cpu(oldv);
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}
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#else
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{
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uintptr_t ra = GETPC();
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx);
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oldv = helper_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra);
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}
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#endif
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if (oldv == cmpv) {
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eflags |= CC_Z;
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} else {
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env->regs[R_EAX] = (uint32_t)oldv;
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env->regs[R_EDX] = (uint32_t)(oldv >> 32);
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eflags &= ~CC_Z;
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}
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CC_SRC = eflags;
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#else
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cpu_loop_exit_atomic(env_cpu(env), GETPC());
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#endif /* CONFIG_ATOMIC64 */
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}
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#ifdef TARGET_X86_64
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void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0)
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{
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uintptr_t ra = GETPC();
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Int128 oldv, cmpv, newv;
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uint64_t o0, o1;
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int eflags;
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bool success;
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if ((a0 & 0xf) != 0) {
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raise_exception_ra(env, EXCP0D_GPF, GETPC());
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}
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eflags = cpu_cc_compute_all(env, CC_OP);
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cmpv = int128_make128(env->regs[R_EAX], env->regs[R_EDX]);
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newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]);
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o0 = cpu_ldq_data_ra(env, a0 + 0, ra);
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o1 = cpu_ldq_data_ra(env, a0 + 8, ra);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (!success) {
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newv = oldv;
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}
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cpu_stq_data_ra(env, a0 + 0, int128_getlo(newv), ra);
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cpu_stq_data_ra(env, a0 + 8, int128_gethi(newv), ra);
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if (success) {
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eflags |= CC_Z;
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} else {
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env->regs[R_EAX] = int128_getlo(oldv);
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env->regs[R_EDX] = int128_gethi(oldv);
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eflags &= ~CC_Z;
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}
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CC_SRC = eflags;
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}
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void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
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{
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uintptr_t ra = GETPC();
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if ((a0 & 0xf) != 0) {
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raise_exception_ra(env, EXCP0D_GPF, ra);
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} else if (HAVE_CMPXCHG128) {
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int eflags = cpu_cc_compute_all(env, CC_OP);
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Int128 cmpv = int128_make128(env->regs[R_EAX], env->regs[R_EDX]);
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Int128 newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]);
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
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Int128 oldv = helper_atomic_cmpxchgo_le_mmu(env, a0, cmpv,
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newv, oi, ra);
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if (int128_eq(oldv, cmpv)) {
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eflags |= CC_Z;
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} else {
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env->regs[R_EAX] = int128_getlo(oldv);
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env->regs[R_EDX] = int128_gethi(oldv);
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eflags &= ~CC_Z;
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}
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CC_SRC = eflags;
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} else {
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cpu_loop_exit_atomic(env_cpu(env), ra);
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}
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}
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#endif
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void helper_boundw(CPUX86State *env, target_ulong a0, int v)
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{
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int low, high;
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low = cpu_ldsw_data_ra(env, a0, GETPC());
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high = cpu_ldsw_data_ra(env, a0 + 2, GETPC());
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v = (int16_t)v;
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if (v < low || v > high) {
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if (env->hflags & HF_MPX_EN_MASK) {
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env->bndcs_regs.sts = 0;
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}
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raise_exception_ra(env, EXCP05_BOUND, GETPC());
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}
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}
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void helper_boundl(CPUX86State *env, target_ulong a0, int v)
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{
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int low, high;
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low = cpu_ldl_data_ra(env, a0, GETPC());
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high = cpu_ldl_data_ra(env, a0 + 4, GETPC());
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if (v < low || v > high) {
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if (env->hflags & HF_MPX_EN_MASK) {
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env->bndcs_regs.sts = 0;
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}
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raise_exception_ra(env, EXCP05_BOUND, GETPC());
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}
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}
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