Use the machine properties instead. Cc: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
638 lines
20 KiB
C
638 lines
20 KiB
C
/*
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* s390x exception / interrupt helpers
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*
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* Copyright (c) 2009 Ulrich Hecht
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* Copyright (c) 2011 Alexander Graf
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internal.h"
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#include "exec/helper-proto.h"
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#include "qemu/timer.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "hw/s390x/ioinst.h"
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#include "exec/address-spaces.h"
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#include "tcg_s390x.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu/sysemu.h"
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#include "hw/s390x/s390_flic.h"
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#include "hw/boards.h"
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#endif
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void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env,
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uint32_t code, uintptr_t ra)
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{
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CPUState *cs = env_cpu(env);
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cpu_restore_state(cs, ra, true);
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qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
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env->psw.addr);
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trigger_pgm_exception(env, code);
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cpu_loop_exit(cs);
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}
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void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc,
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uintptr_t ra)
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{
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g_assert(dxc <= 0xff);
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#if !defined(CONFIG_USER_ONLY)
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/* Store the DXC into the lowcore */
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stl_phys(env_cpu(env)->as,
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env->psa + offsetof(LowCore, data_exc_code), dxc);
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#endif
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/* Store the DXC into the FPC if AFP is enabled */
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if (env->cregs[0] & CR0_AFP) {
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env->fpc = deposit32(env->fpc, 8, 8, dxc);
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}
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tcg_s390_program_interrupt(env, PGM_DATA, ra);
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}
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void QEMU_NORETURN tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc,
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uintptr_t ra)
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{
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g_assert(vxc <= 0xff);
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#if !defined(CONFIG_USER_ONLY)
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/* Always store the VXC into the lowcore, without AFP it is undefined */
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stl_phys(env_cpu(env)->as,
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env->psa + offsetof(LowCore, data_exc_code), vxc);
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#endif
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/* Always store the VXC into the FPC, without AFP it is undefined */
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env->fpc = deposit32(env->fpc, 8, 8, vxc);
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tcg_s390_program_interrupt(env, PGM_VECTOR_PROCESSING, ra);
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}
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void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc)
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{
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tcg_s390_data_exception(env, dxc, GETPC());
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}
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#if defined(CONFIG_USER_ONLY)
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void s390_cpu_do_interrupt(CPUState *cs)
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{
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cs->exception_index = -1;
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}
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bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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S390CPU *cpu = S390_CPU(cs);
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trigger_pgm_exception(&cpu->env, PGM_ADDRESSING);
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/* On real machines this value is dropped into LowMem. Since this
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is userland, simply put this someplace that cpu_loop can find it. */
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cpu->env.__excp_addr = address;
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cpu_loop_exit_restore(cs, retaddr);
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}
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#else /* !CONFIG_USER_ONLY */
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static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
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{
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switch (mmu_idx) {
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case MMU_PRIMARY_IDX:
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return PSW_ASC_PRIMARY;
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case MMU_SECONDARY_IDX:
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return PSW_ASC_SECONDARY;
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case MMU_HOME_IDX:
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return PSW_ASC_HOME;
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default:
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abort();
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}
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}
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bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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target_ulong vaddr, raddr;
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uint64_t asc, tec;
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int prot, excp;
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qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n",
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__func__, address, access_type, mmu_idx);
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vaddr = address;
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if (mmu_idx < MMU_REAL_IDX) {
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asc = cpu_mmu_idx_to_asc(mmu_idx);
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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vaddr &= 0x7fffffff;
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}
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excp = mmu_translate(env, vaddr, access_type, asc, &raddr, &prot, &tec);
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} else if (mmu_idx == MMU_REAL_IDX) {
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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vaddr &= 0x7fffffff;
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}
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excp = mmu_translate_real(env, vaddr, access_type, &raddr, &prot, &tec);
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} else {
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g_assert_not_reached();
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}
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/* check out of RAM access */
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if (!excp &&
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!address_space_access_valid(&address_space_memory, raddr,
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TARGET_PAGE_SIZE, access_type,
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MEMTXATTRS_UNSPECIFIED)) {
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MachineState *ms = MACHINE(qdev_get_machine());
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qemu_log_mask(CPU_LOG_MMU,
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"%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n",
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__func__, (uint64_t)raddr, (uint64_t)ms->ram_size);
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excp = PGM_ADDRESSING;
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tec = 0; /* unused */
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}
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if (!excp) {
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qemu_log_mask(CPU_LOG_MMU,
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"%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n",
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__func__, (uint64_t)vaddr, (uint64_t)raddr, prot);
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tlb_set_page(cs, address & TARGET_PAGE_MASK, raddr, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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if (probe) {
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return false;
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}
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if (excp != PGM_ADDRESSING) {
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stq_phys(env_cpu(env)->as,
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env->psa + offsetof(LowCore, trans_exc_code), tec);
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}
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/*
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* For data accesses, ILEN will be filled in from the unwind info,
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* within cpu_loop_exit_restore. For code accesses, retaddr == 0,
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* and so unwinding will not occur. However, ILEN is also undefined
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* for that case -- we choose to set ILEN = 2.
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*/
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env->int_pgm_ilen = 2;
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trigger_pgm_exception(env, excp);
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cpu_loop_exit_restore(cs, retaddr);
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}
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static void do_program_interrupt(CPUS390XState *env)
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{
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uint64_t mask, addr;
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LowCore *lowcore;
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int ilen = env->int_pgm_ilen;
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assert(ilen == 2 || ilen == 4 || ilen == 6);
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switch (env->int_pgm_code) {
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case PGM_PER:
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if (env->per_perc_atmid & PER_CODE_EVENT_NULLIFICATION) {
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break;
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}
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/* FALL THROUGH */
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case PGM_OPERATION:
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case PGM_PRIVILEGED:
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case PGM_EXECUTE:
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case PGM_PROTECTION:
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case PGM_ADDRESSING:
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case PGM_SPECIFICATION:
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case PGM_DATA:
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case PGM_FIXPT_OVERFLOW:
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case PGM_FIXPT_DIVIDE:
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case PGM_DEC_OVERFLOW:
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case PGM_DEC_DIVIDE:
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case PGM_HFP_EXP_OVERFLOW:
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case PGM_HFP_EXP_UNDERFLOW:
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case PGM_HFP_SIGNIFICANCE:
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case PGM_HFP_DIVIDE:
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case PGM_TRANS_SPEC:
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case PGM_SPECIAL_OP:
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case PGM_OPERAND:
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case PGM_HFP_SQRT:
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case PGM_PC_TRANS_SPEC:
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case PGM_ALET_SPEC:
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case PGM_MONITOR:
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/* advance the PSW if our exception is not nullifying */
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env->psw.addr += ilen;
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break;
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}
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qemu_log_mask(CPU_LOG_INT,
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"%s: code=0x%x ilen=%d psw: %" PRIx64 " %" PRIx64 "\n",
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__func__, env->int_pgm_code, ilen, env->psw.mask,
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env->psw.addr);
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lowcore = cpu_map_lowcore(env);
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/* Signal PER events with the exception. */
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if (env->per_perc_atmid) {
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env->int_pgm_code |= PGM_PER;
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lowcore->per_address = cpu_to_be64(env->per_address);
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lowcore->per_perc_atmid = cpu_to_be16(env->per_perc_atmid);
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env->per_perc_atmid = 0;
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}
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lowcore->pgm_ilen = cpu_to_be16(ilen);
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lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
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lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
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mask = be64_to_cpu(lowcore->program_new_psw.mask);
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addr = be64_to_cpu(lowcore->program_new_psw.addr);
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lowcore->per_breaking_event_addr = cpu_to_be64(env->gbea);
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cpu_unmap_lowcore(lowcore);
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load_psw(env, mask, addr);
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}
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static void do_svc_interrupt(CPUS390XState *env)
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{
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uint64_t mask, addr;
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LowCore *lowcore;
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lowcore = cpu_map_lowcore(env);
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lowcore->svc_code = cpu_to_be16(env->int_svc_code);
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lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen);
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lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen);
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mask = be64_to_cpu(lowcore->svc_new_psw.mask);
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addr = be64_to_cpu(lowcore->svc_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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load_psw(env, mask, addr);
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/* When a PER event is pending, the PER exception has to happen
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immediately after the SERVICE CALL one. */
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if (env->per_perc_atmid) {
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env->int_pgm_code = PGM_PER;
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env->int_pgm_ilen = env->int_svc_ilen;
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do_program_interrupt(env);
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}
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}
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#define VIRTIO_SUBCODE_64 0x0D00
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static void do_ext_interrupt(CPUS390XState *env)
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{
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QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic());
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S390CPU *cpu = env_archcpu(env);
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uint64_t mask, addr;
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uint16_t cpu_addr;
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LowCore *lowcore;
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if (!(env->psw.mask & PSW_MASK_EXT)) {
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cpu_abort(CPU(cpu), "Ext int w/o ext mask\n");
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}
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lowcore = cpu_map_lowcore(env);
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if ((env->pending_int & INTERRUPT_EMERGENCY_SIGNAL) &&
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(env->cregs[0] & CR0_EMERGENCY_SIGNAL_SC)) {
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MachineState *ms = MACHINE(qdev_get_machine());
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unsigned int max_cpus = ms->smp.max_cpus;
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lowcore->ext_int_code = cpu_to_be16(EXT_EMERGENCY);
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cpu_addr = find_first_bit(env->emergency_signals, S390_MAX_CPUS);
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g_assert(cpu_addr < S390_MAX_CPUS);
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lowcore->cpu_addr = cpu_to_be16(cpu_addr);
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clear_bit(cpu_addr, env->emergency_signals);
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if (bitmap_empty(env->emergency_signals, max_cpus)) {
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env->pending_int &= ~INTERRUPT_EMERGENCY_SIGNAL;
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}
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} else if ((env->pending_int & INTERRUPT_EXTERNAL_CALL) &&
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(env->cregs[0] & CR0_EXTERNAL_CALL_SC)) {
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lowcore->ext_int_code = cpu_to_be16(EXT_EXTERNAL_CALL);
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lowcore->cpu_addr = cpu_to_be16(env->external_call_addr);
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env->pending_int &= ~INTERRUPT_EXTERNAL_CALL;
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} else if ((env->pending_int & INTERRUPT_EXT_CLOCK_COMPARATOR) &&
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(env->cregs[0] & CR0_CKC_SC)) {
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lowcore->ext_int_code = cpu_to_be16(EXT_CLOCK_COMP);
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lowcore->cpu_addr = 0;
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env->pending_int &= ~INTERRUPT_EXT_CLOCK_COMPARATOR;
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} else if ((env->pending_int & INTERRUPT_EXT_CPU_TIMER) &&
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(env->cregs[0] & CR0_CPU_TIMER_SC)) {
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lowcore->ext_int_code = cpu_to_be16(EXT_CPU_TIMER);
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lowcore->cpu_addr = 0;
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env->pending_int &= ~INTERRUPT_EXT_CPU_TIMER;
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} else if (qemu_s390_flic_has_service(flic) &&
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(env->cregs[0] & CR0_SERVICE_SC)) {
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uint32_t param;
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param = qemu_s390_flic_dequeue_service(flic);
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lowcore->ext_int_code = cpu_to_be16(EXT_SERVICE);
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lowcore->ext_params = cpu_to_be32(param);
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lowcore->cpu_addr = 0;
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} else {
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g_assert_not_reached();
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}
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mask = be64_to_cpu(lowcore->external_new_psw.mask);
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addr = be64_to_cpu(lowcore->external_new_psw.addr);
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lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
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cpu_unmap_lowcore(lowcore);
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load_psw(env, mask, addr);
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}
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static void do_io_interrupt(CPUS390XState *env)
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{
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QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic());
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uint64_t mask, addr;
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QEMUS390FlicIO *io;
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LowCore *lowcore;
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g_assert(env->psw.mask & PSW_MASK_IO);
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io = qemu_s390_flic_dequeue_io(flic, env->cregs[6]);
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g_assert(io);
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lowcore = cpu_map_lowcore(env);
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lowcore->subchannel_id = cpu_to_be16(io->id);
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lowcore->subchannel_nr = cpu_to_be16(io->nr);
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lowcore->io_int_parm = cpu_to_be32(io->parm);
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lowcore->io_int_word = cpu_to_be32(io->word);
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lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr);
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mask = be64_to_cpu(lowcore->io_new_psw.mask);
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addr = be64_to_cpu(lowcore->io_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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g_free(io);
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load_psw(env, mask, addr);
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}
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typedef struct MchkExtSaveArea {
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uint64_t vregs[32][2]; /* 0x0000 */
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uint8_t pad_0x0200[0x0400 - 0x0200]; /* 0x0200 */
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} MchkExtSaveArea;
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QEMU_BUILD_BUG_ON(sizeof(MchkExtSaveArea) != 1024);
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static int mchk_store_vregs(CPUS390XState *env, uint64_t mcesao)
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{
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hwaddr len = sizeof(MchkExtSaveArea);
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MchkExtSaveArea *sa;
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int i;
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sa = cpu_physical_memory_map(mcesao, &len, true);
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if (!sa) {
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return -EFAULT;
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}
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if (len != sizeof(MchkExtSaveArea)) {
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cpu_physical_memory_unmap(sa, len, 1, 0);
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return -EFAULT;
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}
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for (i = 0; i < 32; i++) {
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sa->vregs[i][0] = cpu_to_be64(env->vregs[i][0]);
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sa->vregs[i][1] = cpu_to_be64(env->vregs[i][1]);
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}
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cpu_physical_memory_unmap(sa, len, 1, len);
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return 0;
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}
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static void do_mchk_interrupt(CPUS390XState *env)
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{
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QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic());
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uint64_t mcic = s390_build_validity_mcic() | MCIC_SC_CP;
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uint64_t mask, addr, mcesao = 0;
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LowCore *lowcore;
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int i;
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/* for now we only support channel report machine checks (floating) */
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g_assert(env->psw.mask & PSW_MASK_MCHECK);
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g_assert(env->cregs[14] & CR14_CHANNEL_REPORT_SC);
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qemu_s390_flic_dequeue_crw_mchk(flic);
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lowcore = cpu_map_lowcore(env);
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/* extended save area */
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if (mcic & MCIC_VB_VR) {
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/* length and alignment is 1024 bytes */
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mcesao = be64_to_cpu(lowcore->mcesad) & ~0x3ffull;
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}
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/* try to store vector registers */
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if (!mcesao || mchk_store_vregs(env, mcesao)) {
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mcic &= ~MCIC_VB_VR;
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}
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/* we are always in z/Architecture mode */
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lowcore->ar_access_id = 1;
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
lowcore->floating_pt_save_area[i] = cpu_to_be64(*get_freg(env, i));
|
|
lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]);
|
|
lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]);
|
|
lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]);
|
|
}
|
|
lowcore->prefixreg_save_area = cpu_to_be32(env->psa);
|
|
lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc);
|
|
lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr);
|
|
lowcore->cpu_timer_save_area = cpu_to_be64(env->cputm);
|
|
lowcore->clock_comp_save_area = cpu_to_be64(env->ckc >> 8);
|
|
|
|
lowcore->mcic = cpu_to_be64(mcic);
|
|
lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env));
|
|
lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr);
|
|
mask = be64_to_cpu(lowcore->mcck_new_psw.mask);
|
|
addr = be64_to_cpu(lowcore->mcck_new_psw.addr);
|
|
|
|
cpu_unmap_lowcore(lowcore);
|
|
|
|
load_psw(env, mask, addr);
|
|
}
|
|
|
|
void s390_cpu_do_interrupt(CPUState *cs)
|
|
{
|
|
QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic());
|
|
S390CPU *cpu = S390_CPU(cs);
|
|
CPUS390XState *env = &cpu->env;
|
|
bool stopped = false;
|
|
|
|
qemu_log_mask(CPU_LOG_INT, "%s: %d at psw=%" PRIx64 ":%" PRIx64 "\n",
|
|
__func__, cs->exception_index, env->psw.mask, env->psw.addr);
|
|
|
|
try_deliver:
|
|
/* handle machine checks */
|
|
if (cs->exception_index == -1 && s390_cpu_has_mcck_int(cpu)) {
|
|
cs->exception_index = EXCP_MCHK;
|
|
}
|
|
/* handle external interrupts */
|
|
if (cs->exception_index == -1 && s390_cpu_has_ext_int(cpu)) {
|
|
cs->exception_index = EXCP_EXT;
|
|
}
|
|
/* handle I/O interrupts */
|
|
if (cs->exception_index == -1 && s390_cpu_has_io_int(cpu)) {
|
|
cs->exception_index = EXCP_IO;
|
|
}
|
|
/* RESTART interrupt */
|
|
if (cs->exception_index == -1 && s390_cpu_has_restart_int(cpu)) {
|
|
cs->exception_index = EXCP_RESTART;
|
|
}
|
|
/* STOP interrupt has least priority */
|
|
if (cs->exception_index == -1 && s390_cpu_has_stop_int(cpu)) {
|
|
cs->exception_index = EXCP_STOP;
|
|
}
|
|
|
|
switch (cs->exception_index) {
|
|
case EXCP_PGM:
|
|
do_program_interrupt(env);
|
|
break;
|
|
case EXCP_SVC:
|
|
do_svc_interrupt(env);
|
|
break;
|
|
case EXCP_EXT:
|
|
do_ext_interrupt(env);
|
|
break;
|
|
case EXCP_IO:
|
|
do_io_interrupt(env);
|
|
break;
|
|
case EXCP_MCHK:
|
|
do_mchk_interrupt(env);
|
|
break;
|
|
case EXCP_RESTART:
|
|
do_restart_interrupt(env);
|
|
break;
|
|
case EXCP_STOP:
|
|
do_stop_interrupt(env);
|
|
stopped = true;
|
|
break;
|
|
}
|
|
|
|
if (cs->exception_index != -1 && !stopped) {
|
|
/* check if there are more pending interrupts to deliver */
|
|
cs->exception_index = -1;
|
|
goto try_deliver;
|
|
}
|
|
cs->exception_index = -1;
|
|
|
|
/* we might still have pending interrupts, but not deliverable */
|
|
if (!env->pending_int && !qemu_s390_flic_has_any(flic)) {
|
|
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
}
|
|
|
|
/* WAIT PSW during interrupt injection or STOP interrupt */
|
|
if ((env->psw.mask & PSW_MASK_WAIT) || stopped) {
|
|
/* don't trigger a cpu_loop_exit(), use an interrupt instead */
|
|
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HALT);
|
|
} else if (cs->halted) {
|
|
/* unhalt if we had a WAIT PSW somehwere in our injection chain */
|
|
s390_cpu_unhalt(cpu);
|
|
}
|
|
}
|
|
|
|
bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
{
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
S390CPU *cpu = S390_CPU(cs);
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
if (env->ex_value) {
|
|
/* Execution of the target insn is indivisible from
|
|
the parent EXECUTE insn. */
|
|
return false;
|
|
}
|
|
if (s390_cpu_has_int(cpu)) {
|
|
s390_cpu_do_interrupt(cs);
|
|
return true;
|
|
}
|
|
if (env->psw.mask & PSW_MASK_WAIT) {
|
|
/* Woken up because of a floating interrupt but it has already
|
|
* been delivered. Go back to sleep. */
|
|
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HALT);
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void s390x_cpu_debug_excp_handler(CPUState *cs)
|
|
{
|
|
S390CPU *cpu = S390_CPU(cs);
|
|
CPUS390XState *env = &cpu->env;
|
|
CPUWatchpoint *wp_hit = cs->watchpoint_hit;
|
|
|
|
if (wp_hit && wp_hit->flags & BP_CPU) {
|
|
/* FIXME: When the storage-alteration-space control bit is set,
|
|
the exception should only be triggered if the memory access
|
|
is done using an address space with the storage-alteration-event
|
|
bit set. We have no way to detect that with the current
|
|
watchpoint code. */
|
|
cs->watchpoint_hit = NULL;
|
|
|
|
env->per_address = env->psw.addr;
|
|
env->per_perc_atmid |= PER_CODE_EVENT_STORE | get_per_atmid(env);
|
|
/* FIXME: We currently no way to detect the address space used
|
|
to trigger the watchpoint. For now just consider it is the
|
|
current default ASC. This turn to be true except when MVCP
|
|
and MVCS instrutions are not used. */
|
|
env->per_perc_atmid |= env->psw.mask & (PSW_MASK_ASC) >> 46;
|
|
|
|
/* Remove all watchpoints to re-execute the code. A PER exception
|
|
will be triggered, it will call load_psw which will recompute
|
|
the watchpoints. */
|
|
cpu_watchpoint_remove_all(cs, BP_CPU);
|
|
cpu_loop_exit_noexc(cs);
|
|
}
|
|
}
|
|
|
|
/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment,
|
|
this is only for the atomic operations, for which we want to raise a
|
|
specification exception. */
|
|
void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
|
|
MMUAccessType access_type,
|
|
int mmu_idx, uintptr_t retaddr)
|
|
{
|
|
S390CPU *cpu = S390_CPU(cs);
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr);
|
|
}
|
|
|
|
static void QEMU_NORETURN monitor_event(CPUS390XState *env,
|
|
uint64_t monitor_code,
|
|
uint8_t monitor_class, uintptr_t ra)
|
|
{
|
|
/* Store the Monitor Code and the Monitor Class Number into the lowcore */
|
|
stq_phys(env_cpu(env)->as,
|
|
env->psa + offsetof(LowCore, monitor_code), monitor_code);
|
|
stw_phys(env_cpu(env)->as,
|
|
env->psa + offsetof(LowCore, mon_class_num), monitor_class);
|
|
|
|
tcg_s390_program_interrupt(env, PGM_MONITOR, ra);
|
|
}
|
|
|
|
void HELPER(monitor_call)(CPUS390XState *env, uint64_t monitor_code,
|
|
uint32_t monitor_class)
|
|
{
|
|
g_assert(monitor_class <= 0xff);
|
|
|
|
if (env->cregs[8] & (0x8000 >> monitor_class)) {
|
|
monitor_event(env, monitor_code, monitor_class, GETPC());
|
|
}
|
|
}
|
|
|
|
#endif /* CONFIG_USER_ONLY */
|