Callers don't really need to know how 64-bit MMU model enums are computed. Hide this in a helper. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20201209173536.1437351-3-groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
1258 lines
36 KiB
C
1258 lines
36 KiB
C
/*
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* PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright (c) 2013 David Gibson, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "qemu/error-report.h"
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#include "qemu/qemu-print.h"
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#include "sysemu/hw_accel.h"
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#include "kvm_ppc.h"
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#include "mmu-hash64.h"
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#include "exec/log.h"
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#include "hw/hw.h"
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#include "mmu-book3s-v3.h"
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/* #define DEBUG_SLB */
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#ifdef DEBUG_SLB
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# define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
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#else
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# define LOG_SLB(...) do { } while (0)
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#endif
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/*
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* SLB handling
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*/
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static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
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{
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CPUPPCState *env = &cpu->env;
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uint64_t esid_256M, esid_1T;
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int n;
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LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
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esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
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esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
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for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
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ppc_slb_t *slb = &env->slb[n];
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LOG_SLB("%s: slot %d %016" PRIx64 " %016"
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PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
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/*
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* We check for 1T matches on all MMUs here - if the MMU
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* doesn't have 1T segment support, we will have prevented 1T
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* entries from being inserted in the slbmte code.
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*/
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if (((slb->esid == esid_256M) &&
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((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
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|| ((slb->esid == esid_1T) &&
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((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
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return slb;
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}
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}
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return NULL;
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}
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void dump_slb(PowerPCCPU *cpu)
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{
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CPUPPCState *env = &cpu->env;
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int i;
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uint64_t slbe, slbv;
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cpu_synchronize_state(CPU(cpu));
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qemu_printf("SLB\tESID\t\t\tVSID\n");
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for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
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slbe = env->slb[i].esid;
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slbv = env->slb[i].vsid;
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if (slbe == 0 && slbv == 0) {
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continue;
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}
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qemu_printf("%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
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i, slbe, slbv);
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}
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}
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void helper_slbia(CPUPPCState *env, uint32_t ih)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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int starting_entry;
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int n;
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/*
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* slbia must always flush all TLB (which is equivalent to ERAT in ppc
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* architecture). Matching on SLB_ESID_V is not good enough, because slbmte
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* can overwrite a valid SLB without flushing its lookaside information.
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*
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* It would be possible to keep the TLB in synch with the SLB by flushing
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* when a valid entry is overwritten by slbmte, and therefore slbia would
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* not have to flush unless it evicts a valid SLB entry. However it is
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* expected that slbmte is more common than slbia, and slbia is usually
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* going to evict valid SLB entries, so that tradeoff is unlikely to be a
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* good one.
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*
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* ISA v2.05 introduced IH field with values 0,1,2,6. These all invalidate
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* the same SLB entries (everything but entry 0), but differ in what
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* "lookaside information" is invalidated. TCG can ignore this and flush
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* everything.
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*
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* ISA v3.0 introduced additional values 3,4,7, which change what SLBs are
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* invalidated.
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*/
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env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
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starting_entry = 1; /* default for IH=0,1,2,6 */
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if (env->mmu_model == POWERPC_MMU_3_00) {
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switch (ih) {
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case 0x7:
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/* invalidate no SLBs, but all lookaside information */
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return;
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case 0x3:
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case 0x4:
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/* also considers SLB entry 0 */
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starting_entry = 0;
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break;
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case 0x5:
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/* treat undefined values as ih==0, and warn */
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qemu_log_mask(LOG_GUEST_ERROR,
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"slbia undefined IH field %u.\n", ih);
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break;
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default:
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/* 0,1,2,6 */
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break;
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}
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}
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for (n = starting_entry; n < cpu->hash64_opts->slb_size; n++) {
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ppc_slb_t *slb = &env->slb[n];
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if (!(slb->esid & SLB_ESID_V)) {
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continue;
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}
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if (env->mmu_model == POWERPC_MMU_3_00) {
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if (ih == 0x3 && (slb->vsid & SLB_VSID_C) == 0) {
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/* preserves entries with a class value of 0 */
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continue;
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}
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}
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slb->esid &= ~SLB_ESID_V;
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}
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}
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static void __helper_slbie(CPUPPCState *env, target_ulong addr,
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target_ulong global)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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ppc_slb_t *slb;
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slb = slb_lookup(cpu, addr);
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if (!slb) {
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return;
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}
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if (slb->esid & SLB_ESID_V) {
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slb->esid &= ~SLB_ESID_V;
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/*
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* XXX: given the fact that segment size is 256 MB or 1TB,
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* and we still don't have a tlb_flush_mask(env, n, mask)
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* in QEMU, we just invalidate all TLBs
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*/
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env->tlb_need_flush |=
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(global == false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_FLUSH);
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}
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}
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void helper_slbie(CPUPPCState *env, target_ulong addr)
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{
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__helper_slbie(env, addr, false);
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}
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void helper_slbieg(CPUPPCState *env, target_ulong addr)
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{
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__helper_slbie(env, addr, true);
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}
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int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
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target_ulong esid, target_ulong vsid)
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{
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CPUPPCState *env = &cpu->env;
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ppc_slb_t *slb = &env->slb[slot];
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const PPCHash64SegmentPageSizes *sps = NULL;
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int i;
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if (slot >= cpu->hash64_opts->slb_size) {
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return -1; /* Bad slot number */
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}
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if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) {
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return -1; /* Reserved bits set */
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}
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if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
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return -1; /* Bad segment size */
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}
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if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) {
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return -1; /* 1T segment on MMU that doesn't support it */
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}
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for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
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const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i];
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if (!sps1->page_shift) {
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break;
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}
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if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
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sps = sps1;
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break;
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}
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}
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if (!sps) {
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error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
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" esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx,
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slot, esid, vsid);
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return -1;
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}
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slb->esid = esid;
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slb->vsid = vsid;
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slb->sps = sps;
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LOG_SLB("%s: " TARGET_FMT_lu " " TARGET_FMT_lx " - " TARGET_FMT_lx
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" => %016" PRIx64 " %016" PRIx64 "\n", __func__, slot, esid, vsid,
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slb->esid, slb->vsid);
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return 0;
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}
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static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
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target_ulong *rt)
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{
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CPUPPCState *env = &cpu->env;
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int slot = rb & 0xfff;
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ppc_slb_t *slb = &env->slb[slot];
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if (slot >= cpu->hash64_opts->slb_size) {
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return -1;
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}
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*rt = slb->esid;
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return 0;
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}
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static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
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target_ulong *rt)
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{
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CPUPPCState *env = &cpu->env;
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int slot = rb & 0xfff;
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ppc_slb_t *slb = &env->slb[slot];
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if (slot >= cpu->hash64_opts->slb_size) {
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return -1;
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}
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*rt = slb->vsid;
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return 0;
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}
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static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
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target_ulong *rt)
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{
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CPUPPCState *env = &cpu->env;
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ppc_slb_t *slb;
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if (!msr_is_64bit(env, env->msr)) {
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rb &= 0xffffffff;
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}
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slb = slb_lookup(cpu, rb);
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if (slb == NULL) {
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*rt = (target_ulong)-1ul;
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} else {
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*rt = slb->vsid;
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}
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return 0;
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}
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void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL, GETPC());
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}
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}
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target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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target_ulong rt = 0;
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if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL, GETPC());
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}
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return rt;
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}
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target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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target_ulong rt = 0;
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if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL, GETPC());
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}
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return rt;
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}
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target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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target_ulong rt = 0;
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if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL, GETPC());
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}
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return rt;
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}
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/* Check No-Execute or Guarded Storage */
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static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
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ppc_hash_pte64_t pte)
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{
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/* Exec permissions CANNOT take away read or write permissions */
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return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ?
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PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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}
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/* Check Basic Storage Protection */
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static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
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ppc_slb_t *slb, ppc_hash_pte64_t pte)
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{
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CPUPPCState *env = &cpu->env;
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unsigned pp, key;
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/*
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* Some pp bit combinations have undefined behaviour, so default
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* to no access in those cases
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*/
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int prot = 0;
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key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
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: (slb->vsid & SLB_VSID_KS));
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pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
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if (key == 0) {
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switch (pp) {
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case 0x0:
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case 0x1:
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case 0x2:
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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break;
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case 0x3:
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case 0x6:
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prot = PAGE_READ | PAGE_EXEC;
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break;
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}
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} else {
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switch (pp) {
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case 0x0:
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case 0x6:
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break;
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case 0x1:
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case 0x3:
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prot = PAGE_READ | PAGE_EXEC;
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break;
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case 0x2:
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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break;
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}
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}
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return prot;
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}
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/* Check the instruction access permissions specified in the IAMR */
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static int ppc_hash64_iamr_prot(PowerPCCPU *cpu, int key)
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{
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CPUPPCState *env = &cpu->env;
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int iamr_bits = (env->spr[SPR_IAMR] >> 2 * (31 - key)) & 0x3;
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/*
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* An instruction fetch is permitted if the IAMR bit is 0.
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* If the bit is set, return PAGE_READ | PAGE_WRITE because this bit
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* can only take away EXEC permissions not READ or WRITE permissions.
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* If bit is cleared return PAGE_READ | PAGE_WRITE | PAGE_EXEC since
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* EXEC permissions are allowed.
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*/
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return (iamr_bits & 0x1) ? PAGE_READ | PAGE_WRITE :
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PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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}
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static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
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{
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CPUPPCState *env = &cpu->env;
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int key, amrbits;
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int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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/* Only recent MMUs implement Virtual Page Class Key Protection */
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if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) {
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return prot;
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}
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key = HPTE64_R_KEY(pte.pte1);
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amrbits = (env->spr[SPR_AMR] >> 2 * (31 - key)) & 0x3;
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/* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
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/* env->spr[SPR_AMR]); */
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/*
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* A store is permitted if the AMR bit is 0. Remove write
|
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* protection if it is set.
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*/
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if (amrbits & 0x2) {
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prot &= ~PAGE_WRITE;
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}
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/*
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* A load is permitted if the AMR bit is 0. Remove read
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* protection if it is set.
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*/
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if (amrbits & 0x1) {
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prot &= ~PAGE_READ;
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}
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|
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switch (env->mmu_model) {
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/*
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* MMU version 2.07 and later support IAMR
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* Check if the IAMR allows the instruction access - it will return
|
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* PAGE_EXEC if it doesn't (and thus that bit will be cleared) or 0
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* if it does (and prot will be unchanged indicating execution support).
|
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*/
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case POWERPC_MMU_2_07:
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case POWERPC_MMU_3_00:
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prot &= ppc_hash64_iamr_prot(cpu, key);
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break;
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default:
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break;
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}
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return prot;
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}
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|
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const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
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hwaddr ptex, int n)
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{
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hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
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hwaddr base;
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hwaddr plen = n * HASH_PTE_SIZE_64;
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const ppc_hash_pte64_t *hptes;
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|
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if (cpu->vhyp) {
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PPCVirtualHypervisorClass *vhc =
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PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
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return vhc->map_hptes(cpu->vhyp, ptex, n);
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}
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base = ppc_hash64_hpt_base(cpu);
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|
|
if (!base) {
|
|
return NULL;
|
|
}
|
|
|
|
hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
|
|
MEMTXATTRS_UNSPECIFIED);
|
|
if (plen < (n * HASH_PTE_SIZE_64)) {
|
|
hw_error("%s: Unable to map all requested HPTEs\n", __func__);
|
|
}
|
|
return hptes;
|
|
}
|
|
|
|
void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
|
|
hwaddr ptex, int n)
|
|
{
|
|
if (cpu->vhyp) {
|
|
PPCVirtualHypervisorClass *vhc =
|
|
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
|
vhc->unmap_hptes(cpu->vhyp, hptes, ptex, n);
|
|
return;
|
|
}
|
|
|
|
address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64,
|
|
false, n * HASH_PTE_SIZE_64);
|
|
}
|
|
|
|
static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps,
|
|
uint64_t pte0, uint64_t pte1)
|
|
{
|
|
int i;
|
|
|
|
if (!(pte0 & HPTE64_V_LARGE)) {
|
|
if (sps->page_shift != 12) {
|
|
/* 4kiB page in a non 4kiB segment */
|
|
return 0;
|
|
}
|
|
/* Normal 4kiB page */
|
|
return 12;
|
|
}
|
|
|
|
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
|
|
const PPCHash64PageSize *ps = &sps->enc[i];
|
|
uint64_t mask;
|
|
|
|
if (!ps->page_shift) {
|
|
break;
|
|
}
|
|
|
|
if (ps->page_shift == 12) {
|
|
/* L bit is set so this can't be a 4kiB page */
|
|
continue;
|
|
}
|
|
|
|
mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
|
|
|
|
if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
|
|
return ps->page_shift;
|
|
}
|
|
}
|
|
|
|
return 0; /* Bad page size encoding */
|
|
}
|
|
|
|
static void ppc64_v3_new_to_old_hpte(target_ulong *pte0, target_ulong *pte1)
|
|
{
|
|
/* Insert B into pte0 */
|
|
*pte0 = (*pte0 & HPTE64_V_COMMON_BITS) |
|
|
((*pte1 & HPTE64_R_3_0_SSIZE_MASK) <<
|
|
(HPTE64_V_SSIZE_SHIFT - HPTE64_R_3_0_SSIZE_SHIFT));
|
|
|
|
/* Remove B from pte1 */
|
|
*pte1 = *pte1 & ~HPTE64_R_3_0_SSIZE_MASK;
|
|
}
|
|
|
|
|
|
static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
|
|
const PPCHash64SegmentPageSizes *sps,
|
|
target_ulong ptem,
|
|
ppc_hash_pte64_t *pte, unsigned *pshift)
|
|
{
|
|
int i;
|
|
const ppc_hash_pte64_t *pteg;
|
|
target_ulong pte0, pte1;
|
|
target_ulong ptex;
|
|
|
|
ptex = (hash & ppc_hash64_hpt_mask(cpu)) * HPTES_PER_GROUP;
|
|
pteg = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
|
|
if (!pteg) {
|
|
return -1;
|
|
}
|
|
for (i = 0; i < HPTES_PER_GROUP; i++) {
|
|
pte0 = ppc_hash64_hpte0(cpu, pteg, i);
|
|
/*
|
|
* pte0 contains the valid bit and must be read before pte1,
|
|
* otherwise we might see an old pte1 with a new valid bit and
|
|
* thus an inconsistent hpte value
|
|
*/
|
|
smp_rmb();
|
|
pte1 = ppc_hash64_hpte1(cpu, pteg, i);
|
|
|
|
/* Convert format if necessary */
|
|
if (cpu->env.mmu_model == POWERPC_MMU_3_00 && !cpu->vhyp) {
|
|
ppc64_v3_new_to_old_hpte(&pte0, &pte1);
|
|
}
|
|
|
|
/* This compares V, B, H (secondary) and the AVPN */
|
|
if (HPTE64_V_COMPARE(pte0, ptem)) {
|
|
*pshift = hpte_page_shift(sps, pte0, pte1);
|
|
/*
|
|
* If there is no match, ignore the PTE, it could simply
|
|
* be for a different segment size encoding and the
|
|
* architecture specifies we should not match. Linux will
|
|
* potentially leave behind PTEs for the wrong base page
|
|
* size when demoting segments.
|
|
*/
|
|
if (*pshift == 0) {
|
|
continue;
|
|
}
|
|
/*
|
|
* We don't do anything with pshift yet as qemu TLB only
|
|
* deals with 4K pages anyway
|
|
*/
|
|
pte->pte0 = pte0;
|
|
pte->pte1 = pte1;
|
|
ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP);
|
|
return ptex + i;
|
|
}
|
|
}
|
|
ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP);
|
|
/*
|
|
* We didn't find a valid entry.
|
|
*/
|
|
return -1;
|
|
}
|
|
|
|
static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
|
|
ppc_slb_t *slb, target_ulong eaddr,
|
|
ppc_hash_pte64_t *pte, unsigned *pshift)
|
|
{
|
|
CPUPPCState *env = &cpu->env;
|
|
hwaddr hash, ptex;
|
|
uint64_t vsid, epnmask, epn, ptem;
|
|
const PPCHash64SegmentPageSizes *sps = slb->sps;
|
|
|
|
/*
|
|
* The SLB store path should prevent any bad page size encodings
|
|
* getting in there, so:
|
|
*/
|
|
assert(sps);
|
|
|
|
/* If ISL is set in LPCR we need to clamp the page size to 4K */
|
|
if (env->spr[SPR_LPCR] & LPCR_ISL) {
|
|
/* We assume that when using TCG, 4k is first entry of SPS */
|
|
sps = &cpu->hash64_opts->sps[0];
|
|
assert(sps->page_shift == 12);
|
|
}
|
|
|
|
epnmask = ~((1ULL << sps->page_shift) - 1);
|
|
|
|
if (slb->vsid & SLB_VSID_B) {
|
|
/* 1TB segment */
|
|
vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
|
|
epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
|
|
hash = vsid ^ (vsid << 25) ^ (epn >> sps->page_shift);
|
|
} else {
|
|
/* 256M segment */
|
|
vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
|
|
epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
|
|
hash = vsid ^ (epn >> sps->page_shift);
|
|
}
|
|
ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
|
|
ptem |= HPTE64_V_VALID;
|
|
|
|
/* Page address translation */
|
|
qemu_log_mask(CPU_LOG_MMU,
|
|
"htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
|
|
" hash " TARGET_FMT_plx "\n",
|
|
ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash);
|
|
|
|
/* Primary PTEG lookup */
|
|
qemu_log_mask(CPU_LOG_MMU,
|
|
"0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
|
|
" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
|
|
" hash=" TARGET_FMT_plx "\n",
|
|
ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu),
|
|
vsid, ptem, hash);
|
|
ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift);
|
|
|
|
if (ptex == -1) {
|
|
/* Secondary PTEG lookup */
|
|
ptem |= HPTE64_V_SECONDARY;
|
|
qemu_log_mask(CPU_LOG_MMU,
|
|
"1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
|
|
" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
|
|
" hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu),
|
|
ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash);
|
|
|
|
ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift);
|
|
}
|
|
|
|
return ptex;
|
|
}
|
|
|
|
unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
|
|
uint64_t pte0, uint64_t pte1)
|
|
{
|
|
int i;
|
|
|
|
if (!(pte0 & HPTE64_V_LARGE)) {
|
|
return 12;
|
|
}
|
|
|
|
/*
|
|
* The encodings in env->sps need to be carefully chosen so that
|
|
* this gives an unambiguous result.
|
|
*/
|
|
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
|
|
const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i];
|
|
unsigned shift;
|
|
|
|
if (!sps->page_shift) {
|
|
break;
|
|
}
|
|
|
|
shift = hpte_page_shift(sps, pte0, pte1);
|
|
if (shift) {
|
|
return shift;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool ppc_hash64_use_vrma(CPUPPCState *env)
|
|
{
|
|
switch (env->mmu_model) {
|
|
case POWERPC_MMU_3_00:
|
|
/*
|
|
* ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR
|
|
* register no longer exist
|
|
*/
|
|
return true;
|
|
|
|
default:
|
|
return !!(env->spr[SPR_LPCR] & LPCR_VPM0);
|
|
}
|
|
}
|
|
|
|
static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code)
|
|
{
|
|
CPUPPCState *env = &POWERPC_CPU(cs)->env;
|
|
bool vpm;
|
|
|
|
if (msr_ir) {
|
|
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
|
|
} else {
|
|
vpm = ppc_hash64_use_vrma(env);
|
|
}
|
|
if (vpm && !msr_hv) {
|
|
cs->exception_index = POWERPC_EXCP_HISI;
|
|
} else {
|
|
cs->exception_index = POWERPC_EXCP_ISI;
|
|
}
|
|
env->error_code = error_code;
|
|
}
|
|
|
|
static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr)
|
|
{
|
|
CPUPPCState *env = &POWERPC_CPU(cs)->env;
|
|
bool vpm;
|
|
|
|
if (msr_dr) {
|
|
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
|
|
} else {
|
|
vpm = ppc_hash64_use_vrma(env);
|
|
}
|
|
if (vpm && !msr_hv) {
|
|
cs->exception_index = POWERPC_EXCP_HDSI;
|
|
env->spr[SPR_HDAR] = dar;
|
|
env->spr[SPR_HDSISR] = dsisr;
|
|
} else {
|
|
cs->exception_index = POWERPC_EXCP_DSI;
|
|
env->spr[SPR_DAR] = dar;
|
|
env->spr[SPR_DSISR] = dsisr;
|
|
}
|
|
env->error_code = 0;
|
|
}
|
|
|
|
|
|
static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
|
|
{
|
|
hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 16;
|
|
|
|
if (cpu->vhyp) {
|
|
PPCVirtualHypervisorClass *vhc =
|
|
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
|
vhc->hpte_set_r(cpu->vhyp, ptex, pte1);
|
|
return;
|
|
}
|
|
base = ppc_hash64_hpt_base(cpu);
|
|
|
|
|
|
/* The HW performs a non-atomic byte update */
|
|
stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
|
|
}
|
|
|
|
static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
|
|
{
|
|
hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 15;
|
|
|
|
if (cpu->vhyp) {
|
|
PPCVirtualHypervisorClass *vhc =
|
|
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
|
vhc->hpte_set_c(cpu->vhyp, ptex, pte1);
|
|
return;
|
|
}
|
|
base = ppc_hash64_hpt_base(cpu);
|
|
|
|
/* The HW performs a non-atomic byte update */
|
|
stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
|
|
}
|
|
|
|
static target_ulong rmls_limit(PowerPCCPU *cpu)
|
|
{
|
|
CPUPPCState *env = &cpu->env;
|
|
/*
|
|
* In theory the meanings of RMLS values are implementation
|
|
* dependent. In practice, this seems to have been the set from
|
|
* POWER4+..POWER8, and RMLS is no longer supported in POWER9.
|
|
*
|
|
* Unsupported values mean the OS has shot itself in the
|
|
* foot. Return a 0-sized RMA in this case, which we expect
|
|
* to trigger an immediate DSI or ISI
|
|
*/
|
|
static const target_ulong rma_sizes[16] = {
|
|
[0] = 256 * GiB,
|
|
[1] = 16 * GiB,
|
|
[2] = 1 * GiB,
|
|
[3] = 64 * MiB,
|
|
[4] = 256 * MiB,
|
|
[7] = 128 * MiB,
|
|
[8] = 32 * MiB,
|
|
};
|
|
target_ulong rmls = (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SHIFT;
|
|
|
|
return rma_sizes[rmls];
|
|
}
|
|
|
|
static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
|
|
{
|
|
CPUPPCState *env = &cpu->env;
|
|
target_ulong lpcr = env->spr[SPR_LPCR];
|
|
uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
|
|
target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK);
|
|
int i;
|
|
|
|
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
|
|
const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i];
|
|
|
|
if (!sps->page_shift) {
|
|
break;
|
|
}
|
|
|
|
if ((vsid & SLB_VSID_LLP_MASK) == sps->slb_enc) {
|
|
slb->esid = SLB_ESID_V;
|
|
slb->vsid = vsid;
|
|
slb->sps = sps;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x"
|
|
TARGET_FMT_lx, lpcr);
|
|
|
|
return -1;
|
|
}
|
|
|
|
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
|
|
int rwx, int mmu_idx)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
CPUPPCState *env = &cpu->env;
|
|
ppc_slb_t vrma_slbe;
|
|
ppc_slb_t *slb;
|
|
unsigned apshift;
|
|
hwaddr ptex;
|
|
ppc_hash_pte64_t pte;
|
|
int exec_prot, pp_prot, amr_prot, prot;
|
|
const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
|
|
hwaddr raddr;
|
|
|
|
assert((rwx == 0) || (rwx == 1) || (rwx == 2));
|
|
|
|
/*
|
|
* Note on LPCR usage: 970 uses HID4, but our special variant of
|
|
* store_spr copies relevant fields into env->spr[SPR_LPCR].
|
|
* Similarly we filter unimplemented bits when storing into LPCR
|
|
* depending on the MMU version. This code can thus just use the
|
|
* LPCR "as-is".
|
|
*/
|
|
|
|
/* 1. Handle real mode accesses */
|
|
if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
|
|
/*
|
|
* Translation is supposedly "off", but in real mode the top 4
|
|
* effective address bits are (mostly) ignored
|
|
*/
|
|
raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
|
|
|
|
if (cpu->vhyp) {
|
|
/*
|
|
* In virtual hypervisor mode, there's nothing to do:
|
|
* EA == GPA == qemu guest address
|
|
*/
|
|
} else if (msr_hv || !env->has_hv_mode) {
|
|
/* In HV mode, add HRMOR if top EA bit is clear */
|
|
if (!(eaddr >> 63)) {
|
|
raddr |= env->spr[SPR_HRMOR];
|
|
}
|
|
} else if (ppc_hash64_use_vrma(env)) {
|
|
/* Emulated VRMA mode */
|
|
slb = &vrma_slbe;
|
|
if (build_vrma_slbe(cpu, slb) != 0) {
|
|
/* Invalid VRMA setup, machine check */
|
|
cs->exception_index = POWERPC_EXCP_MCHECK;
|
|
env->error_code = 0;
|
|
return 1;
|
|
}
|
|
|
|
goto skip_slb_search;
|
|
} else {
|
|
target_ulong limit = rmls_limit(cpu);
|
|
|
|
/* Emulated old-style RMO mode, bounds check against RMLS */
|
|
if (raddr >= limit) {
|
|
if (rwx == 2) {
|
|
ppc_hash64_set_isi(cs, SRR1_PROTFAULT);
|
|
} else {
|
|
int dsisr = DSISR_PROTFAULT;
|
|
if (rwx == 1) {
|
|
dsisr |= DSISR_ISSTORE;
|
|
}
|
|
ppc_hash64_set_dsi(cs, eaddr, dsisr);
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
raddr |= env->spr[SPR_RMOR];
|
|
}
|
|
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
|
|
PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
|
|
TARGET_PAGE_SIZE);
|
|
return 0;
|
|
}
|
|
|
|
/* 2. Translation is on, so look up the SLB */
|
|
slb = slb_lookup(cpu, eaddr);
|
|
if (!slb) {
|
|
/* No entry found, check if in-memory segment tables are in use */
|
|
if (ppc64_use_proc_tbl(cpu)) {
|
|
/* TODO - Unsupported */
|
|
error_report("Segment Table Support Unimplemented");
|
|
exit(1);
|
|
}
|
|
/* Segment still not found, generate the appropriate interrupt */
|
|
if (rwx == 2) {
|
|
cs->exception_index = POWERPC_EXCP_ISEG;
|
|
env->error_code = 0;
|
|
} else {
|
|
cs->exception_index = POWERPC_EXCP_DSEG;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = eaddr;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
skip_slb_search:
|
|
|
|
/* 3. Check for segment level no-execute violation */
|
|
if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
|
|
ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD);
|
|
return 1;
|
|
}
|
|
|
|
/* 4. Locate the PTE in the hash table */
|
|
ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
|
|
if (ptex == -1) {
|
|
if (rwx == 2) {
|
|
ppc_hash64_set_isi(cs, SRR1_NOPTE);
|
|
} else {
|
|
int dsisr = DSISR_NOPTE;
|
|
if (rwx == 1) {
|
|
dsisr |= DSISR_ISSTORE;
|
|
}
|
|
ppc_hash64_set_dsi(cs, eaddr, dsisr);
|
|
}
|
|
return 1;
|
|
}
|
|
qemu_log_mask(CPU_LOG_MMU,
|
|
"found PTE at index %08" HWADDR_PRIx "\n", ptex);
|
|
|
|
/* 5. Check access permissions */
|
|
|
|
exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte);
|
|
pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
|
|
amr_prot = ppc_hash64_amr_prot(cpu, pte);
|
|
prot = exec_prot & pp_prot & amr_prot;
|
|
|
|
if ((need_prot[rwx] & ~prot) != 0) {
|
|
/* Access right violation */
|
|
qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
|
|
if (rwx == 2) {
|
|
int srr1 = 0;
|
|
if (PAGE_EXEC & ~exec_prot) {
|
|
srr1 |= SRR1_NOEXEC_GUARD; /* Access violates noexec or guard */
|
|
} else if (PAGE_EXEC & ~pp_prot) {
|
|
srr1 |= SRR1_PROTFAULT; /* Access violates access authority */
|
|
}
|
|
if (PAGE_EXEC & ~amr_prot) {
|
|
srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */
|
|
}
|
|
ppc_hash64_set_isi(cs, srr1);
|
|
} else {
|
|
int dsisr = 0;
|
|
if (need_prot[rwx] & ~pp_prot) {
|
|
dsisr |= DSISR_PROTFAULT;
|
|
}
|
|
if (rwx == 1) {
|
|
dsisr |= DSISR_ISSTORE;
|
|
}
|
|
if (need_prot[rwx] & ~amr_prot) {
|
|
dsisr |= DSISR_AMR;
|
|
}
|
|
ppc_hash64_set_dsi(cs, eaddr, dsisr);
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
|
|
|
|
/* 6. Update PTE referenced and changed bits if necessary */
|
|
|
|
if (!(pte.pte1 & HPTE64_R_R)) {
|
|
ppc_hash64_set_r(cpu, ptex, pte.pte1);
|
|
}
|
|
if (!(pte.pte1 & HPTE64_R_C)) {
|
|
if (rwx == 1) {
|
|
ppc_hash64_set_c(cpu, ptex, pte.pte1);
|
|
} else {
|
|
/*
|
|
* Treat the page as read-only for now, so that a later write
|
|
* will pass through this function again to set the C bit
|
|
*/
|
|
prot &= ~PAGE_WRITE;
|
|
}
|
|
}
|
|
|
|
/* 7. Determine the real address from the PTE */
|
|
|
|
raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
|
|
|
|
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
|
|
prot, mmu_idx, 1ULL << apshift);
|
|
|
|
return 0;
|
|
}
|
|
|
|
hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
|
|
{
|
|
CPUPPCState *env = &cpu->env;
|
|
ppc_slb_t vrma_slbe;
|
|
ppc_slb_t *slb;
|
|
hwaddr ptex, raddr;
|
|
ppc_hash_pte64_t pte;
|
|
unsigned apshift;
|
|
|
|
/* Handle real mode */
|
|
if (msr_dr == 0) {
|
|
/* In real mode the top 4 effective address bits are ignored */
|
|
raddr = addr & 0x0FFFFFFFFFFFFFFFULL;
|
|
|
|
if (cpu->vhyp) {
|
|
/*
|
|
* In virtual hypervisor mode, there's nothing to do:
|
|
* EA == GPA == qemu guest address
|
|
*/
|
|
return raddr;
|
|
} else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) {
|
|
/* In HV mode, add HRMOR if top EA bit is clear */
|
|
return raddr | env->spr[SPR_HRMOR];
|
|
} else if (ppc_hash64_use_vrma(env)) {
|
|
/* Emulated VRMA mode */
|
|
slb = &vrma_slbe;
|
|
if (build_vrma_slbe(cpu, slb) != 0) {
|
|
return -1;
|
|
}
|
|
} else {
|
|
target_ulong limit = rmls_limit(cpu);
|
|
|
|
/* Emulated old-style RMO mode, bounds check against RMLS */
|
|
if (raddr >= limit) {
|
|
return -1;
|
|
}
|
|
return raddr | env->spr[SPR_RMOR];
|
|
}
|
|
} else {
|
|
slb = slb_lookup(cpu, addr);
|
|
if (!slb) {
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
ptex = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift);
|
|
if (ptex == -1) {
|
|
return -1;
|
|
}
|
|
|
|
return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
|
|
& TARGET_PAGE_MASK;
|
|
}
|
|
|
|
void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
|
|
target_ulong pte0, target_ulong pte1)
|
|
{
|
|
/*
|
|
* XXX: given the fact that there are too many segments to
|
|
* invalidate, and we still don't have a tlb_flush_mask(env, n,
|
|
* mask) in QEMU, we just invalidate all TLBs
|
|
*/
|
|
cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
|
|
}
|
|
|
|
void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
|
|
{
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
|
|
}
|
|
|
|
void helper_store_lpcr(CPUPPCState *env, target_ulong val)
|
|
{
|
|
PowerPCCPU *cpu = env_archcpu(env);
|
|
|
|
ppc_store_lpcr(cpu, val);
|
|
}
|
|
|
|
void ppc_hash64_init(PowerPCCPU *cpu)
|
|
{
|
|
CPUPPCState *env = &cpu->env;
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
|
|
|
if (!pcc->hash64_opts) {
|
|
assert(!mmu_is_64bit(env->mmu_model));
|
|
return;
|
|
}
|
|
|
|
cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts));
|
|
}
|
|
|
|
void ppc_hash64_finalize(PowerPCCPU *cpu)
|
|
{
|
|
g_free(cpu->hash64_opts);
|
|
}
|
|
|
|
const PPCHash64Options ppc_hash64_opts_basic = {
|
|
.flags = 0,
|
|
.slb_size = 64,
|
|
.sps = {
|
|
{ .page_shift = 12, /* 4K */
|
|
.slb_enc = 0,
|
|
.enc = { { .page_shift = 12, .pte_enc = 0 } }
|
|
},
|
|
{ .page_shift = 24, /* 16M */
|
|
.slb_enc = 0x100,
|
|
.enc = { { .page_shift = 24, .pte_enc = 0 } }
|
|
},
|
|
},
|
|
};
|
|
|
|
const PPCHash64Options ppc_hash64_opts_POWER7 = {
|
|
.flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE,
|
|
.slb_size = 32,
|
|
.sps = {
|
|
{
|
|
.page_shift = 12, /* 4K */
|
|
.slb_enc = 0,
|
|
.enc = { { .page_shift = 12, .pte_enc = 0 },
|
|
{ .page_shift = 16, .pte_enc = 0x7 },
|
|
{ .page_shift = 24, .pte_enc = 0x38 }, },
|
|
},
|
|
{
|
|
.page_shift = 16, /* 64K */
|
|
.slb_enc = SLB_VSID_64K,
|
|
.enc = { { .page_shift = 16, .pte_enc = 0x1 },
|
|
{ .page_shift = 24, .pte_enc = 0x8 }, },
|
|
},
|
|
{
|
|
.page_shift = 24, /* 16M */
|
|
.slb_enc = SLB_VSID_16M,
|
|
.enc = { { .page_shift = 24, .pte_enc = 0 }, },
|
|
},
|
|
{
|
|
.page_shift = 34, /* 16G */
|
|
.slb_enc = SLB_VSID_16G,
|
|
.enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
|
|
},
|
|
}
|
|
};
|
|
|
|
void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
|
|
bool (*cb)(void *, uint32_t, uint32_t),
|
|
void *opaque)
|
|
{
|
|
PPCHash64Options *opts = cpu->hash64_opts;
|
|
int i;
|
|
int n = 0;
|
|
bool ci_largepage = false;
|
|
|
|
assert(opts);
|
|
|
|
n = 0;
|
|
for (i = 0; i < ARRAY_SIZE(opts->sps); i++) {
|
|
PPCHash64SegmentPageSizes *sps = &opts->sps[i];
|
|
int j;
|
|
int m = 0;
|
|
|
|
assert(n <= i);
|
|
|
|
if (!sps->page_shift) {
|
|
break;
|
|
}
|
|
|
|
for (j = 0; j < ARRAY_SIZE(sps->enc); j++) {
|
|
PPCHash64PageSize *ps = &sps->enc[j];
|
|
|
|
assert(m <= j);
|
|
if (!ps->page_shift) {
|
|
break;
|
|
}
|
|
|
|
if (cb(opaque, sps->page_shift, ps->page_shift)) {
|
|
if (ps->page_shift >= 16) {
|
|
ci_largepage = true;
|
|
}
|
|
sps->enc[m++] = *ps;
|
|
}
|
|
}
|
|
|
|
/* Clear rest of the row */
|
|
for (j = m; j < ARRAY_SIZE(sps->enc); j++) {
|
|
memset(&sps->enc[j], 0, sizeof(sps->enc[j]));
|
|
}
|
|
|
|
if (m) {
|
|
n++;
|
|
}
|
|
}
|
|
|
|
/* Clear the rest of the table */
|
|
for (i = n; i < ARRAY_SIZE(opts->sps); i++) {
|
|
memset(&opts->sps[i], 0, sizeof(opts->sps[i]));
|
|
}
|
|
|
|
if (!ci_largepage) {
|
|
opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
|
|
}
|
|
}
|