85fdd74ff0
The NPCM730 and NPCM750 SoCs have three timer modules each holding five timers and some shared registers (e.g. interrupt status). Each timer runs at 25 MHz divided by a prescaler, and counts down from a configurable initial value to zero. When zero is reached, the interrupt flag for the timer is set, and the timer is disabled (one-shot mode) or reloaded from its initial value (periodic mode). This implementation is sufficient to boot a Linux kernel configured for NPCM750. Note that the kernel does not seem to actually turn on the interrupts. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-4-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
94 lines
6 KiB
Plaintext
94 lines
6 KiB
Plaintext
# See docs/devel/tracing.txt for syntax documentation.
|
|
|
|
# slavio_timer.c
|
|
slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit 0x%"PRIx64" count 0x%x0x%08x"
|
|
slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count 0x%x0x%08x"
|
|
slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address 0x%"PRIx64
|
|
slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read 0x%"PRIx64" = 0x%08x"
|
|
slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write 0x%"PRIx64" = 0x%08x"
|
|
slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to 0x%016"PRIx64
|
|
slavio_timer_mem_writel_counter_invalid(void) "not user timer"
|
|
slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started"
|
|
slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped"
|
|
slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer"
|
|
slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter"
|
|
slavio_timer_mem_writel_mode_invalid(void) "not system timer"
|
|
slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address 0x%"PRIx64
|
|
|
|
# grlib_gptimer.c
|
|
grlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run"
|
|
grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x"
|
|
grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x"
|
|
grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq:%uHz"
|
|
grlib_gptimer_hit(int id) "timer:%d HIT"
|
|
grlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
|
|
grlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
|
|
|
|
# lm32_timer.c
|
|
lm32_timer_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
|
|
lm32_timer_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
|
|
lm32_timer_hit(void) "timer hit"
|
|
lm32_timer_irq_state(int level) "irq state %d"
|
|
|
|
# milkymist-sysctl.c
|
|
milkymist_sysctl_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
|
|
milkymist_sysctl_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
|
|
milkymist_sysctl_icap_write(uint32_t value) "value 0x%08x"
|
|
milkymist_sysctl_start_timer0(void) "Start timer0"
|
|
milkymist_sysctl_stop_timer0(void) "Stop timer0"
|
|
milkymist_sysctl_start_timer1(void) "Start timer1"
|
|
milkymist_sysctl_stop_timer1(void) "Stop timer1"
|
|
milkymist_sysctl_pulse_irq_timer0(void) "Pulse IRQ Timer0"
|
|
milkymist_sysctl_pulse_irq_timer1(void) "Pulse IRQ Timer1"
|
|
|
|
# aspeed_timer.c
|
|
aspeed_timer_ctrl_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
|
|
aspeed_timer_ctrl_external_clock(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
|
|
aspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
|
|
aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
|
|
aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32
|
|
aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32
|
|
aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64
|
|
|
|
# armv7m_systick.c
|
|
systick_reload(void) "systick reload"
|
|
systick_timer_tick(void) "systick reload"
|
|
systick_read(uint64_t addr, uint32_t value, unsigned size) "systick read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
|
|
systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
|
|
|
|
# cmsdk-apb-timer.c
|
|
cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
|
cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
|
cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset"
|
|
|
|
# cmsdk-apb-dualtimer.c
|
|
cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
|
cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
|
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
|
|
|
|
# npcm7xx_timer.c
|
|
npcm7xx_timer_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
|
|
npcm7xx_timer_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
|
|
npcm7xx_timer_irq(const char *id, int timer, int state) "%s timer %d state %d"
|
|
|
|
# nrf51_timer.c
|
|
nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
|
|
nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
|
|
nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32
|
|
|
|
# bcm2835_systmr.c
|
|
bcm2835_systmr_irq(bool enable) "timer irq state %u"
|
|
bcm2835_systmr_read(uint64_t offset, uint64_t data) "timer read: offset 0x%" PRIx64 " data 0x%" PRIx64
|
|
bcm2835_systmr_write(uint64_t offset, uint64_t data) "timer write: offset 0x%" PRIx64 " data 0x%" PRIx64
|
|
|
|
# avr_timer16.c
|
|
avr_timer16_read(uint8_t addr, uint8_t value) "timer16 read addr:%u value:%u"
|
|
avr_timer16_read_ifr(uint8_t value) "timer16 read addr:ifr value:%u"
|
|
avr_timer16_read_imsk(uint8_t value) "timer16 read addr:imsk value:%u"
|
|
avr_timer16_write(uint8_t addr, uint8_t value) "timer16 write addr:%u value:%u"
|
|
avr_timer16_write_imsk(uint8_t value) "timer16 write addr:imsk value:%u"
|
|
avr_timer16_interrupt_count(uint8_t cnt) "count: %u"
|
|
avr_timer16_interrupt_overflow(const char *reason) "overflow: %s"
|
|
avr_timer16_next_alarm(uint64_t delay_ns) "next alarm: %" PRIu64 " ns from now"
|
|
avr_timer16_clksrc_update(uint64_t freq_hz, uint64_t period_ns, uint64_t delay_s) "timer frequency: %" PRIu64 " Hz, period: %" PRIu64 " ns (%" PRId64 " us)"
|