dca625768a
Add the Allwinner A10 AHCI controller module to the SoC. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 69d6962f2d14a218bd07e9ac4ccd1947737cc30f.1445917756.git.crosthwaite.peter@gmail.com Signed-off-by: John Snow <jsnow@redhat.com>
43 lines
1,010 B
C
43 lines
1,010 B
C
#ifndef ALLWINNER_H_
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "hw/char/serial.h"
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#include "hw/arm/arm.h"
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#include "hw/timer/allwinner-a10-pit.h"
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#include "hw/intc/allwinner-a10-pic.h"
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#include "hw/net/allwinner_emac.h"
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#include "hw/ide/pci.h"
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#include "hw/ide/ahci.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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#define AW_A10_PIC_REG_BASE 0x01c20400
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#define AW_A10_PIT_REG_BASE 0x01c20c00
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#define AW_A10_UART0_REG_BASE 0x01c28000
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#define AW_A10_EMAC_BASE 0x01c0b000
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#define AW_A10_SATA_BASE 0x01c18000
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#define AW_A10_SDRAM_BASE 0x40000000
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#define TYPE_AW_A10 "allwinner-a10"
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#define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10)
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typedef struct AwA10State {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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ARMCPU cpu;
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qemu_irq irq[AW_A10_PIC_INT_NR];
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AwA10PITState timer;
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AwA10PICState intc;
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AwEmacState emac;
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AllwinnerAHCIState sata;
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} AwA10State;
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#define ALLWINNER_H_
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#endif
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