Shadow registers are part of the openrisc spec along with sr[cid], as part of the fast context switching feature. When exceptions occur, instead of having to save registers to the stack if enabled the CID will increment and a new set of registers will be available. This patch only implements shadow registers which can be used as extra scratch registers via the mfspr and mtspr if required. This is implemented in a way where it would be easy to add on the fast context switching, currently cid is hardcoded to 0. This is need for openrisc linux smp kernels to boot correctly. Signed-off-by: Stafford Horne <shorne@gmail.com>
277 lines
7.5 KiB
C
277 lines
7.5 KiB
C
/*
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* QEMU OpenRISC CPU
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*
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* Copyright (c) 2012 Jia Liu <proljc@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "exec/exec-all.h"
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static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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cpu->env.pc = value;
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}
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static bool openrisc_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & (CPU_INTERRUPT_HARD |
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CPU_INTERRUPT_TIMER);
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}
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/* CPUClass::reset() */
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static void openrisc_cpu_reset(CPUState *s)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(s);
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OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
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occ->parent_reset(s);
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memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
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cpu->env.pc = 0x100;
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cpu->env.sr = SR_FO | SR_SM;
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cpu->env.lock_addr = -1;
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s->exception_index = -1;
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cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
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cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_NSGF;
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cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
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cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
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#ifndef CONFIG_USER_ONLY
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cpu->env.picmr = 0x00000000;
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cpu->env.picsr = 0x00000000;
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cpu->env.ttmr = 0x00000000;
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cpu->env.ttcr = 0x00000000;
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#endif
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}
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static inline void set_feature(OpenRISCCPU *cpu, int feature)
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{
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cpu->feature |= feature;
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cpu->env.cpucfgr = cpu->feature;
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}
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static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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occ->parent_realize(dev, errp);
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}
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static void openrisc_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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static int inited;
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cs->env_ptr = &cpu->env;
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#ifndef CONFIG_USER_ONLY
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cpu_openrisc_mmu_init(cpu);
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#endif
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if (tcg_enabled() && !inited) {
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inited = 1;
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openrisc_translate_init();
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}
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}
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/* CPU models */
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static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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if (cpu_model == NULL) {
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return NULL;
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}
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typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
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object_class_is_abstract(oc))) {
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return NULL;
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}
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return oc;
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}
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static void or1200_initfn(Object *obj)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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set_feature(cpu, OPENRISC_FEATURE_NSGF);
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set_feature(cpu, OPENRISC_FEATURE_OB32S);
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set_feature(cpu, OPENRISC_FEATURE_OF32S);
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set_feature(cpu, OPENRISC_FEATURE_EVBAR);
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}
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static void openrisc_any_initfn(Object *obj)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(obj);
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set_feature(cpu, OPENRISC_FEATURE_NSGF);
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set_feature(cpu, OPENRISC_FEATURE_OB32S);
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set_feature(cpu, OPENRISC_FEATURE_EVBAR);
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}
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typedef struct OpenRISCCPUInfo {
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const char *name;
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void (*initfn)(Object *obj);
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} OpenRISCCPUInfo;
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static const OpenRISCCPUInfo openrisc_cpus[] = {
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{ .name = "or1200", .initfn = or1200_initfn },
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{ .name = "any", .initfn = openrisc_any_initfn },
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};
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static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
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{
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OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(occ);
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DeviceClass *dc = DEVICE_CLASS(oc);
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occ->parent_realize = dc->realize;
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dc->realize = openrisc_cpu_realizefn;
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occ->parent_reset = cc->reset;
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cc->reset = openrisc_cpu_reset;
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cc->class_by_name = openrisc_cpu_class_by_name;
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cc->has_work = openrisc_cpu_has_work;
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cc->do_interrupt = openrisc_cpu_do_interrupt;
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cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
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cc->dump_state = openrisc_cpu_dump_state;
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cc->set_pc = openrisc_cpu_set_pc;
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cc->gdb_read_register = openrisc_cpu_gdb_read_register;
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cc->gdb_write_register = openrisc_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
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#else
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cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
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dc->vmsd = &vmstate_openrisc_cpu;
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#endif
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cc->gdb_num_core_regs = 32 + 3;
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}
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static void cpu_register(const OpenRISCCPUInfo *info)
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{
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TypeInfo type_info = {
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.parent = TYPE_OPENRISC_CPU,
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.instance_size = sizeof(OpenRISCCPU),
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.instance_init = info->initfn,
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.class_size = sizeof(OpenRISCCPUClass),
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};
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type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
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type_register(&type_info);
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g_free((void *)type_info.name);
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}
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static const TypeInfo openrisc_cpu_type_info = {
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.name = TYPE_OPENRISC_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(OpenRISCCPU),
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.instance_init = openrisc_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(OpenRISCCPUClass),
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.class_init = openrisc_cpu_class_init,
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};
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static void openrisc_cpu_register_types(void)
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{
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int i;
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type_register_static(&openrisc_cpu_type_info);
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for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
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cpu_register(&openrisc_cpus[i]);
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}
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}
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OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
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{
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return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
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}
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/* Sort alphabetically by type name, except for "any". */
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static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
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{
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ObjectClass *class_a = (ObjectClass *)a;
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ObjectClass *class_b = (ObjectClass *)b;
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const char *name_a, *name_b;
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name_a = object_class_get_name(class_a);
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name_b = object_class_get_name(class_b);
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if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
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return 1;
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} else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
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return -1;
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} else {
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return strcmp(name_a, name_b);
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}
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}
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static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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CPUListState *s = user_data;
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const char *typename;
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char *name;
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typename = object_class_get_name(oc);
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name = g_strndup(typename,
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strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
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(*s->cpu_fprintf)(s->file, " %s\n",
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name);
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g_free(name);
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}
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void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
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{
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CPUListState s = {
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.file = f,
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.cpu_fprintf = cpu_fprintf,
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};
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GSList *list;
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list = object_class_get_list(TYPE_OPENRISC_CPU, false);
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list = g_slist_sort(list, openrisc_cpu_list_compare);
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(*cpu_fprintf)(f, "Available CPUs:\n");
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g_slist_foreach(list, openrisc_cpu_list_entry, &s);
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g_slist_free(list);
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}
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type_init(openrisc_cpu_register_types)
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