Currently the ptimer design uses a QEMU bottom-half as its mechanism for calling back into the device model using the ptimer when the timer has expired. Unfortunately this design is fatally flawed, because it means that there is a lag between the ptimer updating its own state and the device callback function updating device state, and guest accesses to device registers between the two can return inconsistent device state. We want to replace the bottom-half design with one where the guest device's callback is called either immediately (when the ptimer triggers by timeout) or when the device model code closes a transaction-begin/end section (when the ptimer triggers because the device model changed the ptimer's count value or other state). As the first step, rename ptimer_init() to ptimer_init_with_bh(), to free up the ptimer_init() name for the new API. We can then convert all the ptimer users away from ptimer_init_with_bh() before removing it entirely. (Commit created with git grep -l ptimer_init | xargs sed -i -e 's/ptimer_init/ptimer_init_with_bh/' and three overlong lines folded by hand.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191008171740.9679-2-peter.maydell@linaro.org
167 lines
4.4 KiB
C
167 lines
4.4 KiB
C
/*
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* QEMU model of the Canon DIGIC timer block.
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*
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* Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* This model is based on reverse engineering efforts
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* made by CHDK (http://chdk.wikia.com) and
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* Magic Lantern (http://www.magiclantern.fm) projects
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* contributors.
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*
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* See "Timer/Clock Module" docs here:
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* http://magiclantern.wikia.com/wiki/Register_Map
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*
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* The QEMU model of the OSTimer in PKUnity SoC by Guan Xuetao
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* is used as a template.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/ptimer.h"
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#include "hw/timer/digic-timer.h"
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#include "migration/vmstate.h"
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static const VMStateDescription vmstate_digic_timer = {
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.name = "digic.timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PTIMER(ptimer, DigicTimerState),
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VMSTATE_UINT32(control, DigicTimerState),
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VMSTATE_UINT32(relvalue, DigicTimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void digic_timer_reset(DeviceState *dev)
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{
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DigicTimerState *s = DIGIC_TIMER(dev);
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ptimer_stop(s->ptimer);
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s->control = 0;
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s->relvalue = 0;
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}
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static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size)
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{
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DigicTimerState *s = opaque;
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uint64_t ret = 0;
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switch (offset) {
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case DIGIC_TIMER_CONTROL:
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ret = s->control;
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break;
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case DIGIC_TIMER_RELVALUE:
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ret = s->relvalue;
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break;
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case DIGIC_TIMER_VALUE:
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ret = ptimer_get_count(s->ptimer) & 0xffff;
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"digic-timer: read access to unknown register 0x"
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TARGET_FMT_plx "\n", offset);
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}
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return ret;
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}
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static void digic_timer_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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DigicTimerState *s = opaque;
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switch (offset) {
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case DIGIC_TIMER_CONTROL:
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if (value & DIGIC_TIMER_CONTROL_RST) {
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digic_timer_reset((DeviceState *)s);
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break;
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}
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if (value & DIGIC_TIMER_CONTROL_EN) {
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ptimer_run(s->ptimer, 0);
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}
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s->control = (uint32_t)value;
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break;
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case DIGIC_TIMER_RELVALUE:
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s->relvalue = extract32(value, 0, 16);
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ptimer_set_limit(s->ptimer, s->relvalue, 1);
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break;
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case DIGIC_TIMER_VALUE:
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"digic-timer: read access to unknown register 0x"
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TARGET_FMT_plx "\n", offset);
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}
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}
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static const MemoryRegionOps digic_timer_ops = {
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.read = digic_timer_read,
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.write = digic_timer_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void digic_timer_init(Object *obj)
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{
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DigicTimerState *s = DIGIC_TIMER(obj);
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s->ptimer = ptimer_init_with_bh(NULL, PTIMER_POLICY_DEFAULT);
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/*
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* FIXME: there is no documentation on Digic timer
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* frequency setup so let it always run at 1 MHz
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*/
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ptimer_set_freq(s->ptimer, 1 * 1000 * 1000);
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memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s,
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TYPE_DIGIC_TIMER, 0x100);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
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}
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static void digic_timer_class_init(ObjectClass *klass, void *class_data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = digic_timer_reset;
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dc->vmsd = &vmstate_digic_timer;
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}
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static const TypeInfo digic_timer_info = {
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.name = TYPE_DIGIC_TIMER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(DigicTimerState),
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.instance_init = digic_timer_init,
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.class_init = digic_timer_class_init,
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};
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static void digic_timer_register_type(void)
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{
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type_register_static(&digic_timer_info);
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}
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type_init(digic_timer_register_type)
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