Since 39bffca203
(qdev: register all
types natively through QEMU Object Model), TypeInfo as used in
the common, non-iterative pattern is no longer amended with information
and should therefore be const.
Fix the documented QOM examples:
sed -i 's/static TypeInfo/static const TypeInfo/g' include/qom/object.h
Since frequently the wrong examples are being copied by contributors of
new devices, fix all types in the tree:
sed -i 's/^static TypeInfo/static const TypeInfo/g' */*.c
sed -i 's/^static TypeInfo/static const TypeInfo/g' */*/*.c
This also avoids to piggy-back these changes onto real functional
changes or other refactorings.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
1400 lines
39 KiB
C
1400 lines
39 KiB
C
/*
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* Luminary Micro Stellaris peripherals
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "sysbus.h"
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#include "ssi.h"
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#include "arm-misc.h"
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#include "devices.h"
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#include "qemu/timer.h"
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#include "i2c.h"
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#include "net/net.h"
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#include "boards.h"
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#include "exec/address-spaces.h"
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#define GPIO_A 0
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#define GPIO_B 1
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#define GPIO_C 2
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#define GPIO_D 3
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#define GPIO_E 4
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#define GPIO_F 5
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#define GPIO_G 6
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#define BP_OLED_I2C 0x01
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#define BP_OLED_SSI 0x02
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#define BP_GAMEPAD 0x04
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typedef const struct {
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const char *name;
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uint32_t did0;
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uint32_t did1;
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uint32_t dc0;
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uint32_t dc1;
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uint32_t dc2;
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uint32_t dc3;
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uint32_t dc4;
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uint32_t peripherals;
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} stellaris_board_info;
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/* General purpose timer module. */
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typedef struct gptm_state {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t config;
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uint32_t mode[2];
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uint32_t control;
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uint32_t state;
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uint32_t mask;
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uint32_t load[2];
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uint32_t match[2];
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uint32_t prescale[2];
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uint32_t match_prescale[2];
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uint32_t rtc;
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int64_t tick[2];
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struct gptm_state *opaque[2];
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QEMUTimer *timer[2];
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/* The timers have an alternate output used to trigger the ADC. */
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qemu_irq trigger;
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qemu_irq irq;
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} gptm_state;
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static void gptm_update_irq(gptm_state *s)
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{
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int level;
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level = (s->state & s->mask) != 0;
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qemu_set_irq(s->irq, level);
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}
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static void gptm_stop(gptm_state *s, int n)
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{
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qemu_del_timer(s->timer[n]);
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}
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static void gptm_reload(gptm_state *s, int n, int reset)
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{
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int64_t tick;
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if (reset)
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tick = qemu_get_clock_ns(vm_clock);
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else
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tick = s->tick[n];
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if (s->config == 0) {
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/* 32-bit CountDown. */
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uint32_t count;
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count = s->load[0] | (s->load[1] << 16);
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tick += (int64_t)count * system_clock_scale;
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} else if (s->config == 1) {
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/* 32-bit RTC. 1Hz tick. */
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tick += get_ticks_per_sec();
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} else if (s->mode[n] == 0xa) {
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/* PWM mode. Not implemented. */
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} else {
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hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
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}
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s->tick[n] = tick;
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qemu_mod_timer(s->timer[n], tick);
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}
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static void gptm_tick(void *opaque)
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{
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gptm_state **p = (gptm_state **)opaque;
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gptm_state *s;
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int n;
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s = *p;
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n = p - s->opaque;
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if (s->config == 0) {
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s->state |= 1;
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if ((s->control & 0x20)) {
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/* Output trigger. */
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qemu_irq_pulse(s->trigger);
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}
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if (s->mode[0] & 1) {
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/* One-shot. */
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s->control &= ~1;
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} else {
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/* Periodic. */
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gptm_reload(s, 0, 0);
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}
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} else if (s->config == 1) {
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/* RTC. */
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uint32_t match;
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s->rtc++;
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match = s->match[0] | (s->match[1] << 16);
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if (s->rtc > match)
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s->rtc = 0;
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if (s->rtc == 0) {
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s->state |= 8;
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}
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gptm_reload(s, 0, 0);
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} else if (s->mode[n] == 0xa) {
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/* PWM mode. Not implemented. */
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} else {
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hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
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}
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gptm_update_irq(s);
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}
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static uint64_t gptm_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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gptm_state *s = (gptm_state *)opaque;
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switch (offset) {
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case 0x00: /* CFG */
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return s->config;
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case 0x04: /* TAMR */
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return s->mode[0];
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case 0x08: /* TBMR */
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return s->mode[1];
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case 0x0c: /* CTL */
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return s->control;
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case 0x18: /* IMR */
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return s->mask;
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case 0x1c: /* RIS */
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return s->state;
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case 0x20: /* MIS */
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return s->state & s->mask;
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case 0x24: /* CR */
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return 0;
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case 0x28: /* TAILR */
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return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
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case 0x2c: /* TBILR */
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return s->load[1];
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case 0x30: /* TAMARCHR */
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return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
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case 0x34: /* TBMATCHR */
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return s->match[1];
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case 0x38: /* TAPR */
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return s->prescale[0];
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case 0x3c: /* TBPR */
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return s->prescale[1];
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case 0x40: /* TAPMR */
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return s->match_prescale[0];
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case 0x44: /* TBPMR */
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return s->match_prescale[1];
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case 0x48: /* TAR */
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if (s->control == 1)
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return s->rtc;
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case 0x4c: /* TBR */
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hw_error("TODO: Timer value read\n");
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default:
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hw_error("gptm_read: Bad offset 0x%x\n", (int)offset);
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return 0;
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}
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}
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static void gptm_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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gptm_state *s = (gptm_state *)opaque;
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uint32_t oldval;
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/* The timers should be disabled before changing the configuration.
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We take advantage of this and defer everything until the timer
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is enabled. */
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switch (offset) {
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case 0x00: /* CFG */
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s->config = value;
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break;
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case 0x04: /* TAMR */
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s->mode[0] = value;
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break;
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case 0x08: /* TBMR */
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s->mode[1] = value;
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break;
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case 0x0c: /* CTL */
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oldval = s->control;
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s->control = value;
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/* TODO: Implement pause. */
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if ((oldval ^ value) & 1) {
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if (value & 1) {
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gptm_reload(s, 0, 1);
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} else {
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gptm_stop(s, 0);
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}
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}
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if (((oldval ^ value) & 0x100) && s->config >= 4) {
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if (value & 0x100) {
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gptm_reload(s, 1, 1);
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} else {
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gptm_stop(s, 1);
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}
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}
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break;
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case 0x18: /* IMR */
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s->mask = value & 0x77;
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gptm_update_irq(s);
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break;
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case 0x24: /* CR */
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s->state &= ~value;
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break;
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case 0x28: /* TAILR */
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s->load[0] = value & 0xffff;
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if (s->config < 4) {
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s->load[1] = value >> 16;
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}
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break;
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case 0x2c: /* TBILR */
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s->load[1] = value & 0xffff;
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break;
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case 0x30: /* TAMARCHR */
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s->match[0] = value & 0xffff;
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if (s->config < 4) {
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s->match[1] = value >> 16;
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}
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break;
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case 0x34: /* TBMATCHR */
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s->match[1] = value >> 16;
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break;
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case 0x38: /* TAPR */
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s->prescale[0] = value;
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break;
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case 0x3c: /* TBPR */
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s->prescale[1] = value;
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break;
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case 0x40: /* TAPMR */
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s->match_prescale[0] = value;
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break;
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case 0x44: /* TBPMR */
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s->match_prescale[0] = value;
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break;
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default:
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hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
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}
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gptm_update_irq(s);
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}
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static const MemoryRegionOps gptm_ops = {
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.read = gptm_read,
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.write = gptm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_stellaris_gptm = {
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.name = "stellaris_gptm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(config, gptm_state),
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VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
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VMSTATE_UINT32(control, gptm_state),
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VMSTATE_UINT32(state, gptm_state),
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VMSTATE_UINT32(mask, gptm_state),
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VMSTATE_UNUSED(8),
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VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
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VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
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VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
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VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
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VMSTATE_UINT32(rtc, gptm_state),
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VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
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VMSTATE_TIMER_ARRAY(timer, gptm_state, 2),
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VMSTATE_END_OF_LIST()
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}
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};
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static int stellaris_gptm_init(SysBusDevice *dev)
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{
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gptm_state *s = FROM_SYSBUS(gptm_state, dev);
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sysbus_init_irq(dev, &s->irq);
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qdev_init_gpio_out(&dev->qdev, &s->trigger, 1);
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memory_region_init_io(&s->iomem, &gptm_ops, s,
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"gptm", 0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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s->opaque[0] = s->opaque[1] = s;
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s->timer[0] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[0]);
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s->timer[1] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[1]);
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vmstate_register(&dev->qdev, -1, &vmstate_stellaris_gptm, s);
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return 0;
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}
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/* System controller. */
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typedef struct {
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MemoryRegion iomem;
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uint32_t pborctl;
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uint32_t ldopctl;
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uint32_t int_status;
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uint32_t int_mask;
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uint32_t resc;
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uint32_t rcc;
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uint32_t rcc2;
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uint32_t rcgc[3];
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uint32_t scgc[3];
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uint32_t dcgc[3];
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uint32_t clkvclr;
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uint32_t ldoarst;
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uint32_t user0;
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uint32_t user1;
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qemu_irq irq;
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stellaris_board_info *board;
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} ssys_state;
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static void ssys_update(ssys_state *s)
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{
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qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
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}
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static uint32_t pllcfg_sandstorm[16] = {
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0x31c0, /* 1 Mhz */
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0x1ae0, /* 1.8432 Mhz */
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0x18c0, /* 2 Mhz */
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0xd573, /* 2.4576 Mhz */
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0x37a6, /* 3.57954 Mhz */
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0x1ae2, /* 3.6864 Mhz */
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0x0c40, /* 4 Mhz */
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0x98bc, /* 4.906 Mhz */
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0x935b, /* 4.9152 Mhz */
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0x09c0, /* 5 Mhz */
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0x4dee, /* 5.12 Mhz */
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0x0c41, /* 6 Mhz */
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0x75db, /* 6.144 Mhz */
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0x1ae6, /* 7.3728 Mhz */
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0x0600, /* 8 Mhz */
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0x585b /* 8.192 Mhz */
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};
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static uint32_t pllcfg_fury[16] = {
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0x3200, /* 1 Mhz */
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0x1b20, /* 1.8432 Mhz */
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0x1900, /* 2 Mhz */
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0xf42b, /* 2.4576 Mhz */
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0x37e3, /* 3.57954 Mhz */
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0x1b21, /* 3.6864 Mhz */
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0x0c80, /* 4 Mhz */
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0x98ee, /* 4.906 Mhz */
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0xd5b4, /* 4.9152 Mhz */
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0x0a00, /* 5 Mhz */
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0x4e27, /* 5.12 Mhz */
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0x1902, /* 6 Mhz */
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0xec1c, /* 6.144 Mhz */
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0x1b23, /* 7.3728 Mhz */
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0x0640, /* 8 Mhz */
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0xb11c /* 8.192 Mhz */
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};
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#define DID0_VER_MASK 0x70000000
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#define DID0_VER_0 0x00000000
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#define DID0_VER_1 0x10000000
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#define DID0_CLASS_MASK 0x00FF0000
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#define DID0_CLASS_SANDSTORM 0x00000000
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#define DID0_CLASS_FURY 0x00010000
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static int ssys_board_class(const ssys_state *s)
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{
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uint32_t did0 = s->board->did0;
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switch (did0 & DID0_VER_MASK) {
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case DID0_VER_0:
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return DID0_CLASS_SANDSTORM;
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case DID0_VER_1:
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switch (did0 & DID0_CLASS_MASK) {
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case DID0_CLASS_SANDSTORM:
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case DID0_CLASS_FURY:
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return did0 & DID0_CLASS_MASK;
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}
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/* for unknown classes, fall through */
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default:
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hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
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}
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}
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static uint64_t ssys_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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ssys_state *s = (ssys_state *)opaque;
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switch (offset) {
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case 0x000: /* DID0 */
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return s->board->did0;
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case 0x004: /* DID1 */
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return s->board->did1;
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case 0x008: /* DC0 */
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return s->board->dc0;
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case 0x010: /* DC1 */
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return s->board->dc1;
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case 0x014: /* DC2 */
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return s->board->dc2;
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case 0x018: /* DC3 */
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return s->board->dc3;
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case 0x01c: /* DC4 */
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return s->board->dc4;
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case 0x030: /* PBORCTL */
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return s->pborctl;
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case 0x034: /* LDOPCTL */
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return s->ldopctl;
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case 0x040: /* SRCR0 */
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return 0;
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case 0x044: /* SRCR1 */
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return 0;
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case 0x048: /* SRCR2 */
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return 0;
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case 0x050: /* RIS */
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return s->int_status;
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case 0x054: /* IMC */
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return s->int_mask;
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case 0x058: /* MISC */
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return s->int_status & s->int_mask;
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case 0x05c: /* RESC */
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return s->resc;
|
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case 0x060: /* RCC */
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return s->rcc;
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case 0x064: /* PLLCFG */
|
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{
|
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int xtal;
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xtal = (s->rcc >> 6) & 0xf;
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switch (ssys_board_class(s)) {
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case DID0_CLASS_FURY:
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return pllcfg_fury[xtal];
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case DID0_CLASS_SANDSTORM:
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return pllcfg_sandstorm[xtal];
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default:
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hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
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return 0;
|
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}
|
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}
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case 0x070: /* RCC2 */
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return s->rcc2;
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case 0x100: /* RCGC0 */
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return s->rcgc[0];
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case 0x104: /* RCGC1 */
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return s->rcgc[1];
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case 0x108: /* RCGC2 */
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return s->rcgc[2];
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case 0x110: /* SCGC0 */
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return s->scgc[0];
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case 0x114: /* SCGC1 */
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return s->scgc[1];
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case 0x118: /* SCGC2 */
|
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return s->scgc[2];
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case 0x120: /* DCGC0 */
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return s->dcgc[0];
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case 0x124: /* DCGC1 */
|
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return s->dcgc[1];
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case 0x128: /* DCGC2 */
|
|
return s->dcgc[2];
|
|
case 0x150: /* CLKVCLR */
|
|
return s->clkvclr;
|
|
case 0x160: /* LDOARST */
|
|
return s->ldoarst;
|
|
case 0x1e0: /* USER0 */
|
|
return s->user0;
|
|
case 0x1e4: /* USER1 */
|
|
return s->user1;
|
|
default:
|
|
hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static bool ssys_use_rcc2(ssys_state *s)
|
|
{
|
|
return (s->rcc2 >> 31) & 0x1;
|
|
}
|
|
|
|
/*
|
|
* Caculate the sys. clock period in ms.
|
|
*/
|
|
static void ssys_calculate_system_clock(ssys_state *s)
|
|
{
|
|
if (ssys_use_rcc2(s)) {
|
|
system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
|
|
} else {
|
|
system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
|
|
}
|
|
}
|
|
|
|
static void ssys_write(void *opaque, hwaddr offset,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
ssys_state *s = (ssys_state *)opaque;
|
|
|
|
switch (offset) {
|
|
case 0x030: /* PBORCTL */
|
|
s->pborctl = value & 0xffff;
|
|
break;
|
|
case 0x034: /* LDOPCTL */
|
|
s->ldopctl = value & 0x1f;
|
|
break;
|
|
case 0x040: /* SRCR0 */
|
|
case 0x044: /* SRCR1 */
|
|
case 0x048: /* SRCR2 */
|
|
fprintf(stderr, "Peripheral reset not implemented\n");
|
|
break;
|
|
case 0x054: /* IMC */
|
|
s->int_mask = value & 0x7f;
|
|
break;
|
|
case 0x058: /* MISC */
|
|
s->int_status &= ~value;
|
|
break;
|
|
case 0x05c: /* RESC */
|
|
s->resc = value & 0x3f;
|
|
break;
|
|
case 0x060: /* RCC */
|
|
if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
|
|
/* PLL enable. */
|
|
s->int_status |= (1 << 6);
|
|
}
|
|
s->rcc = value;
|
|
ssys_calculate_system_clock(s);
|
|
break;
|
|
case 0x070: /* RCC2 */
|
|
if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
|
|
break;
|
|
}
|
|
|
|
if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
|
|
/* PLL enable. */
|
|
s->int_status |= (1 << 6);
|
|
}
|
|
s->rcc2 = value;
|
|
ssys_calculate_system_clock(s);
|
|
break;
|
|
case 0x100: /* RCGC0 */
|
|
s->rcgc[0] = value;
|
|
break;
|
|
case 0x104: /* RCGC1 */
|
|
s->rcgc[1] = value;
|
|
break;
|
|
case 0x108: /* RCGC2 */
|
|
s->rcgc[2] = value;
|
|
break;
|
|
case 0x110: /* SCGC0 */
|
|
s->scgc[0] = value;
|
|
break;
|
|
case 0x114: /* SCGC1 */
|
|
s->scgc[1] = value;
|
|
break;
|
|
case 0x118: /* SCGC2 */
|
|
s->scgc[2] = value;
|
|
break;
|
|
case 0x120: /* DCGC0 */
|
|
s->dcgc[0] = value;
|
|
break;
|
|
case 0x124: /* DCGC1 */
|
|
s->dcgc[1] = value;
|
|
break;
|
|
case 0x128: /* DCGC2 */
|
|
s->dcgc[2] = value;
|
|
break;
|
|
case 0x150: /* CLKVCLR */
|
|
s->clkvclr = value;
|
|
break;
|
|
case 0x160: /* LDOARST */
|
|
s->ldoarst = value;
|
|
break;
|
|
default:
|
|
hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
|
|
}
|
|
ssys_update(s);
|
|
}
|
|
|
|
static const MemoryRegionOps ssys_ops = {
|
|
.read = ssys_read,
|
|
.write = ssys_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void ssys_reset(void *opaque)
|
|
{
|
|
ssys_state *s = (ssys_state *)opaque;
|
|
|
|
s->pborctl = 0x7ffd;
|
|
s->rcc = 0x078e3ac0;
|
|
|
|
if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
|
|
s->rcc2 = 0;
|
|
} else {
|
|
s->rcc2 = 0x07802810;
|
|
}
|
|
s->rcgc[0] = 1;
|
|
s->scgc[0] = 1;
|
|
s->dcgc[0] = 1;
|
|
ssys_calculate_system_clock(s);
|
|
}
|
|
|
|
static int stellaris_sys_post_load(void *opaque, int version_id)
|
|
{
|
|
ssys_state *s = opaque;
|
|
|
|
ssys_calculate_system_clock(s);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_stellaris_sys = {
|
|
.name = "stellaris_sys",
|
|
.version_id = 2,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.post_load = stellaris_sys_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(pborctl, ssys_state),
|
|
VMSTATE_UINT32(ldopctl, ssys_state),
|
|
VMSTATE_UINT32(int_mask, ssys_state),
|
|
VMSTATE_UINT32(int_status, ssys_state),
|
|
VMSTATE_UINT32(resc, ssys_state),
|
|
VMSTATE_UINT32(rcc, ssys_state),
|
|
VMSTATE_UINT32_V(rcc2, ssys_state, 2),
|
|
VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
|
|
VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
|
|
VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
|
|
VMSTATE_UINT32(clkvclr, ssys_state),
|
|
VMSTATE_UINT32(ldoarst, ssys_state),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static int stellaris_sys_init(uint32_t base, qemu_irq irq,
|
|
stellaris_board_info * board,
|
|
uint8_t *macaddr)
|
|
{
|
|
ssys_state *s;
|
|
|
|
s = (ssys_state *)g_malloc0(sizeof(ssys_state));
|
|
s->irq = irq;
|
|
s->board = board;
|
|
/* Most devices come preprogrammed with a MAC address in the user data. */
|
|
s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
|
|
s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
|
|
|
|
memory_region_init_io(&s->iomem, &ssys_ops, s, "ssys", 0x00001000);
|
|
memory_region_add_subregion(get_system_memory(), base, &s->iomem);
|
|
ssys_reset(s);
|
|
vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* I2C controller. */
|
|
|
|
typedef struct {
|
|
SysBusDevice busdev;
|
|
i2c_bus *bus;
|
|
qemu_irq irq;
|
|
MemoryRegion iomem;
|
|
uint32_t msa;
|
|
uint32_t mcs;
|
|
uint32_t mdr;
|
|
uint32_t mtpr;
|
|
uint32_t mimr;
|
|
uint32_t mris;
|
|
uint32_t mcr;
|
|
} stellaris_i2c_state;
|
|
|
|
#define STELLARIS_I2C_MCS_BUSY 0x01
|
|
#define STELLARIS_I2C_MCS_ERROR 0x02
|
|
#define STELLARIS_I2C_MCS_ADRACK 0x04
|
|
#define STELLARIS_I2C_MCS_DATACK 0x08
|
|
#define STELLARIS_I2C_MCS_ARBLST 0x10
|
|
#define STELLARIS_I2C_MCS_IDLE 0x20
|
|
#define STELLARIS_I2C_MCS_BUSBSY 0x40
|
|
|
|
static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
|
|
unsigned size)
|
|
{
|
|
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
|
|
|
|
switch (offset) {
|
|
case 0x00: /* MSA */
|
|
return s->msa;
|
|
case 0x04: /* MCS */
|
|
/* We don't emulate timing, so the controller is never busy. */
|
|
return s->mcs | STELLARIS_I2C_MCS_IDLE;
|
|
case 0x08: /* MDR */
|
|
return s->mdr;
|
|
case 0x0c: /* MTPR */
|
|
return s->mtpr;
|
|
case 0x10: /* MIMR */
|
|
return s->mimr;
|
|
case 0x14: /* MRIS */
|
|
return s->mris;
|
|
case 0x18: /* MMIS */
|
|
return s->mris & s->mimr;
|
|
case 0x20: /* MCR */
|
|
return s->mcr;
|
|
default:
|
|
hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static void stellaris_i2c_update(stellaris_i2c_state *s)
|
|
{
|
|
int level;
|
|
|
|
level = (s->mris & s->mimr) != 0;
|
|
qemu_set_irq(s->irq, level);
|
|
}
|
|
|
|
static void stellaris_i2c_write(void *opaque, hwaddr offset,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
|
|
|
|
switch (offset) {
|
|
case 0x00: /* MSA */
|
|
s->msa = value & 0xff;
|
|
break;
|
|
case 0x04: /* MCS */
|
|
if ((s->mcr & 0x10) == 0) {
|
|
/* Disabled. Do nothing. */
|
|
break;
|
|
}
|
|
/* Grab the bus if this is starting a transfer. */
|
|
if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
|
|
if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
|
|
s->mcs |= STELLARIS_I2C_MCS_ARBLST;
|
|
} else {
|
|
s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
|
|
s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
|
|
}
|
|
}
|
|
/* If we don't have the bus then indicate an error. */
|
|
if (!i2c_bus_busy(s->bus)
|
|
|| (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
|
|
s->mcs |= STELLARIS_I2C_MCS_ERROR;
|
|
break;
|
|
}
|
|
s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
|
|
if (value & 1) {
|
|
/* Transfer a byte. */
|
|
/* TODO: Handle errors. */
|
|
if (s->msa & 1) {
|
|
/* Recv */
|
|
s->mdr = i2c_recv(s->bus) & 0xff;
|
|
} else {
|
|
/* Send */
|
|
i2c_send(s->bus, s->mdr);
|
|
}
|
|
/* Raise an interrupt. */
|
|
s->mris |= 1;
|
|
}
|
|
if (value & 4) {
|
|
/* Finish transfer. */
|
|
i2c_end_transfer(s->bus);
|
|
s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
|
|
}
|
|
break;
|
|
case 0x08: /* MDR */
|
|
s->mdr = value & 0xff;
|
|
break;
|
|
case 0x0c: /* MTPR */
|
|
s->mtpr = value & 0xff;
|
|
break;
|
|
case 0x10: /* MIMR */
|
|
s->mimr = 1;
|
|
break;
|
|
case 0x1c: /* MICR */
|
|
s->mris &= ~value;
|
|
break;
|
|
case 0x20: /* MCR */
|
|
if (value & 1)
|
|
hw_error(
|
|
"stellaris_i2c_write: Loopback not implemented\n");
|
|
if (value & 0x20)
|
|
hw_error(
|
|
"stellaris_i2c_write: Slave mode not implemented\n");
|
|
s->mcr = value & 0x31;
|
|
break;
|
|
default:
|
|
hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
|
|
(int)offset);
|
|
}
|
|
stellaris_i2c_update(s);
|
|
}
|
|
|
|
static void stellaris_i2c_reset(stellaris_i2c_state *s)
|
|
{
|
|
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
|
|
i2c_end_transfer(s->bus);
|
|
|
|
s->msa = 0;
|
|
s->mcs = 0;
|
|
s->mdr = 0;
|
|
s->mtpr = 1;
|
|
s->mimr = 0;
|
|
s->mris = 0;
|
|
s->mcr = 0;
|
|
stellaris_i2c_update(s);
|
|
}
|
|
|
|
static const MemoryRegionOps stellaris_i2c_ops = {
|
|
.read = stellaris_i2c_read,
|
|
.write = stellaris_i2c_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static const VMStateDescription vmstate_stellaris_i2c = {
|
|
.name = "stellaris_i2c",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(msa, stellaris_i2c_state),
|
|
VMSTATE_UINT32(mcs, stellaris_i2c_state),
|
|
VMSTATE_UINT32(mdr, stellaris_i2c_state),
|
|
VMSTATE_UINT32(mtpr, stellaris_i2c_state),
|
|
VMSTATE_UINT32(mimr, stellaris_i2c_state),
|
|
VMSTATE_UINT32(mris, stellaris_i2c_state),
|
|
VMSTATE_UINT32(mcr, stellaris_i2c_state),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static int stellaris_i2c_init(SysBusDevice * dev)
|
|
{
|
|
stellaris_i2c_state *s = FROM_SYSBUS(stellaris_i2c_state, dev);
|
|
i2c_bus *bus;
|
|
|
|
sysbus_init_irq(dev, &s->irq);
|
|
bus = i2c_init_bus(&dev->qdev, "i2c");
|
|
s->bus = bus;
|
|
|
|
memory_region_init_io(&s->iomem, &stellaris_i2c_ops, s,
|
|
"i2c", 0x1000);
|
|
sysbus_init_mmio(dev, &s->iomem);
|
|
/* ??? For now we only implement the master interface. */
|
|
stellaris_i2c_reset(s);
|
|
vmstate_register(&dev->qdev, -1, &vmstate_stellaris_i2c, s);
|
|
return 0;
|
|
}
|
|
|
|
/* Analogue to Digital Converter. This is only partially implemented,
|
|
enough for applications that use a combined ADC and timer tick. */
|
|
|
|
#define STELLARIS_ADC_EM_CONTROLLER 0
|
|
#define STELLARIS_ADC_EM_COMP 1
|
|
#define STELLARIS_ADC_EM_EXTERNAL 4
|
|
#define STELLARIS_ADC_EM_TIMER 5
|
|
#define STELLARIS_ADC_EM_PWM0 6
|
|
#define STELLARIS_ADC_EM_PWM1 7
|
|
#define STELLARIS_ADC_EM_PWM2 8
|
|
|
|
#define STELLARIS_ADC_FIFO_EMPTY 0x0100
|
|
#define STELLARIS_ADC_FIFO_FULL 0x1000
|
|
|
|
typedef struct
|
|
{
|
|
SysBusDevice busdev;
|
|
MemoryRegion iomem;
|
|
uint32_t actss;
|
|
uint32_t ris;
|
|
uint32_t im;
|
|
uint32_t emux;
|
|
uint32_t ostat;
|
|
uint32_t ustat;
|
|
uint32_t sspri;
|
|
uint32_t sac;
|
|
struct {
|
|
uint32_t state;
|
|
uint32_t data[16];
|
|
} fifo[4];
|
|
uint32_t ssmux[4];
|
|
uint32_t ssctl[4];
|
|
uint32_t noise;
|
|
qemu_irq irq[4];
|
|
} stellaris_adc_state;
|
|
|
|
static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
|
|
{
|
|
int tail;
|
|
|
|
tail = s->fifo[n].state & 0xf;
|
|
if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
|
|
s->ustat |= 1 << n;
|
|
} else {
|
|
s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
|
|
s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
|
|
if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
|
|
s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
|
|
}
|
|
return s->fifo[n].data[tail];
|
|
}
|
|
|
|
static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
|
|
uint32_t value)
|
|
{
|
|
int head;
|
|
|
|
/* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
|
|
FIFO fir each sequencer. */
|
|
head = (s->fifo[n].state >> 4) & 0xf;
|
|
if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
|
|
s->ostat |= 1 << n;
|
|
return;
|
|
}
|
|
s->fifo[n].data[head] = value;
|
|
head = (head + 1) & 0xf;
|
|
s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
|
|
s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
|
|
if ((s->fifo[n].state & 0xf) == head)
|
|
s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
|
|
}
|
|
|
|
static void stellaris_adc_update(stellaris_adc_state *s)
|
|
{
|
|
int level;
|
|
int n;
|
|
|
|
for (n = 0; n < 4; n++) {
|
|
level = (s->ris & s->im & (1 << n)) != 0;
|
|
qemu_set_irq(s->irq[n], level);
|
|
}
|
|
}
|
|
|
|
static void stellaris_adc_trigger(void *opaque, int irq, int level)
|
|
{
|
|
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
|
|
int n;
|
|
|
|
for (n = 0; n < 4; n++) {
|
|
if ((s->actss & (1 << n)) == 0) {
|
|
continue;
|
|
}
|
|
|
|
if (((s->emux >> (n * 4)) & 0xff) != 5) {
|
|
continue;
|
|
}
|
|
|
|
/* Some applications use the ADC as a random number source, so introduce
|
|
some variation into the signal. */
|
|
s->noise = s->noise * 314159 + 1;
|
|
/* ??? actual inputs not implemented. Return an arbitrary value. */
|
|
stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
|
|
s->ris |= (1 << n);
|
|
stellaris_adc_update(s);
|
|
}
|
|
}
|
|
|
|
static void stellaris_adc_reset(stellaris_adc_state *s)
|
|
{
|
|
int n;
|
|
|
|
for (n = 0; n < 4; n++) {
|
|
s->ssmux[n] = 0;
|
|
s->ssctl[n] = 0;
|
|
s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
|
|
}
|
|
}
|
|
|
|
static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
|
|
unsigned size)
|
|
{
|
|
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
|
|
|
|
/* TODO: Implement this. */
|
|
if (offset >= 0x40 && offset < 0xc0) {
|
|
int n;
|
|
n = (offset - 0x40) >> 5;
|
|
switch (offset & 0x1f) {
|
|
case 0x00: /* SSMUX */
|
|
return s->ssmux[n];
|
|
case 0x04: /* SSCTL */
|
|
return s->ssctl[n];
|
|
case 0x08: /* SSFIFO */
|
|
return stellaris_adc_fifo_read(s, n);
|
|
case 0x0c: /* SSFSTAT */
|
|
return s->fifo[n].state;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
switch (offset) {
|
|
case 0x00: /* ACTSS */
|
|
return s->actss;
|
|
case 0x04: /* RIS */
|
|
return s->ris;
|
|
case 0x08: /* IM */
|
|
return s->im;
|
|
case 0x0c: /* ISC */
|
|
return s->ris & s->im;
|
|
case 0x10: /* OSTAT */
|
|
return s->ostat;
|
|
case 0x14: /* EMUX */
|
|
return s->emux;
|
|
case 0x18: /* USTAT */
|
|
return s->ustat;
|
|
case 0x20: /* SSPRI */
|
|
return s->sspri;
|
|
case 0x30: /* SAC */
|
|
return s->sac;
|
|
default:
|
|
hw_error("strllaris_adc_read: Bad offset 0x%x\n",
|
|
(int)offset);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static void stellaris_adc_write(void *opaque, hwaddr offset,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
|
|
|
|
/* TODO: Implement this. */
|
|
if (offset >= 0x40 && offset < 0xc0) {
|
|
int n;
|
|
n = (offset - 0x40) >> 5;
|
|
switch (offset & 0x1f) {
|
|
case 0x00: /* SSMUX */
|
|
s->ssmux[n] = value & 0x33333333;
|
|
return;
|
|
case 0x04: /* SSCTL */
|
|
if (value != 6) {
|
|
hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
|
|
value);
|
|
}
|
|
s->ssctl[n] = value;
|
|
return;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
switch (offset) {
|
|
case 0x00: /* ACTSS */
|
|
s->actss = value & 0xf;
|
|
break;
|
|
case 0x08: /* IM */
|
|
s->im = value;
|
|
break;
|
|
case 0x0c: /* ISC */
|
|
s->ris &= ~value;
|
|
break;
|
|
case 0x10: /* OSTAT */
|
|
s->ostat &= ~value;
|
|
break;
|
|
case 0x14: /* EMUX */
|
|
s->emux = value;
|
|
break;
|
|
case 0x18: /* USTAT */
|
|
s->ustat &= ~value;
|
|
break;
|
|
case 0x20: /* SSPRI */
|
|
s->sspri = value;
|
|
break;
|
|
case 0x28: /* PSSI */
|
|
hw_error("Not implemented: ADC sample initiate\n");
|
|
break;
|
|
case 0x30: /* SAC */
|
|
s->sac = value;
|
|
break;
|
|
default:
|
|
hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
|
|
}
|
|
stellaris_adc_update(s);
|
|
}
|
|
|
|
static const MemoryRegionOps stellaris_adc_ops = {
|
|
.read = stellaris_adc_read,
|
|
.write = stellaris_adc_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static const VMStateDescription vmstate_stellaris_adc = {
|
|
.name = "stellaris_adc",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(actss, stellaris_adc_state),
|
|
VMSTATE_UINT32(ris, stellaris_adc_state),
|
|
VMSTATE_UINT32(im, stellaris_adc_state),
|
|
VMSTATE_UINT32(emux, stellaris_adc_state),
|
|
VMSTATE_UINT32(ostat, stellaris_adc_state),
|
|
VMSTATE_UINT32(ustat, stellaris_adc_state),
|
|
VMSTATE_UINT32(sspri, stellaris_adc_state),
|
|
VMSTATE_UINT32(sac, stellaris_adc_state),
|
|
VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
|
|
VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
|
|
VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
|
|
VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
|
|
VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
|
|
VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
|
|
VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
|
|
VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
|
|
VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
|
|
VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
|
|
VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
|
|
VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
|
|
VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
|
|
VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
|
|
VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
|
|
VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
|
|
VMSTATE_UINT32(noise, stellaris_adc_state),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static int stellaris_adc_init(SysBusDevice *dev)
|
|
{
|
|
stellaris_adc_state *s = FROM_SYSBUS(stellaris_adc_state, dev);
|
|
int n;
|
|
|
|
for (n = 0; n < 4; n++) {
|
|
sysbus_init_irq(dev, &s->irq[n]);
|
|
}
|
|
|
|
memory_region_init_io(&s->iomem, &stellaris_adc_ops, s,
|
|
"adc", 0x1000);
|
|
sysbus_init_mmio(dev, &s->iomem);
|
|
stellaris_adc_reset(s);
|
|
qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1);
|
|
vmstate_register(&dev->qdev, -1, &vmstate_stellaris_adc, s);
|
|
return 0;
|
|
}
|
|
|
|
/* Board init. */
|
|
static stellaris_board_info stellaris_boards[] = {
|
|
{ "LM3S811EVB",
|
|
0,
|
|
0x0032000e,
|
|
0x001f001f, /* dc0 */
|
|
0x001132bf,
|
|
0x01071013,
|
|
0x3f0f01ff,
|
|
0x0000001f,
|
|
BP_OLED_I2C
|
|
},
|
|
{ "LM3S6965EVB",
|
|
0x10010002,
|
|
0x1073402e,
|
|
0x00ff007f, /* dc0 */
|
|
0x001133ff,
|
|
0x030f5317,
|
|
0x0f0f87ff,
|
|
0x5000007f,
|
|
BP_OLED_SSI | BP_GAMEPAD
|
|
}
|
|
};
|
|
|
|
static void stellaris_init(const char *kernel_filename, const char *cpu_model,
|
|
stellaris_board_info *board)
|
|
{
|
|
static const int uart_irq[] = {5, 6, 33, 34};
|
|
static const int timer_irq[] = {19, 21, 23, 35};
|
|
static const uint32_t gpio_addr[7] =
|
|
{ 0x40004000, 0x40005000, 0x40006000, 0x40007000,
|
|
0x40024000, 0x40025000, 0x40026000};
|
|
static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
|
|
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
qemu_irq *pic;
|
|
DeviceState *gpio_dev[7];
|
|
qemu_irq gpio_in[7][8];
|
|
qemu_irq gpio_out[7][8];
|
|
qemu_irq adc;
|
|
int sram_size;
|
|
int flash_size;
|
|
i2c_bus *i2c;
|
|
DeviceState *dev;
|
|
int i;
|
|
int j;
|
|
|
|
flash_size = ((board->dc0 & 0xffff) + 1) << 1;
|
|
sram_size = (board->dc0 >> 18) + 1;
|
|
pic = armv7m_init(address_space_mem,
|
|
flash_size, sram_size, kernel_filename, cpu_model);
|
|
|
|
if (board->dc1 & (1 << 16)) {
|
|
dev = sysbus_create_varargs("stellaris-adc", 0x40038000,
|
|
pic[14], pic[15], pic[16], pic[17], NULL);
|
|
adc = qdev_get_gpio_in(dev, 0);
|
|
} else {
|
|
adc = NULL;
|
|
}
|
|
for (i = 0; i < 4; i++) {
|
|
if (board->dc2 & (0x10000 << i)) {
|
|
dev = sysbus_create_simple("stellaris-gptm",
|
|
0x40030000 + i * 0x1000,
|
|
pic[timer_irq[i]]);
|
|
/* TODO: This is incorrect, but we get away with it because
|
|
the ADC output is only ever pulsed. */
|
|
qdev_connect_gpio_out(dev, 0, adc);
|
|
}
|
|
}
|
|
|
|
stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr.a);
|
|
|
|
for (i = 0; i < 7; i++) {
|
|
if (board->dc4 & (1 << i)) {
|
|
gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
|
|
pic[gpio_irq[i]]);
|
|
for (j = 0; j < 8; j++) {
|
|
gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
|
|
gpio_out[i][j] = NULL;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (board->dc2 & (1 << 12)) {
|
|
dev = sysbus_create_simple("stellaris-i2c", 0x40020000, pic[8]);
|
|
i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
|
|
if (board->peripherals & BP_OLED_I2C) {
|
|
i2c_create_slave(i2c, "ssd0303", 0x3d);
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
if (board->dc2 & (1 << i)) {
|
|
sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000,
|
|
pic[uart_irq[i]]);
|
|
}
|
|
}
|
|
if (board->dc2 & (1 << 4)) {
|
|
dev = sysbus_create_simple("pl022", 0x40008000, pic[7]);
|
|
if (board->peripherals & BP_OLED_SSI) {
|
|
void *bus;
|
|
DeviceState *sddev;
|
|
DeviceState *ssddev;
|
|
|
|
/* Some boards have both an OLED controller and SD card connected to
|
|
* the same SSI port, with the SD card chip select connected to a
|
|
* GPIO pin. Technically the OLED chip select is connected to the
|
|
* SSI Fss pin. We do not bother emulating that as both devices
|
|
* should never be selected simultaneously, and our OLED controller
|
|
* ignores stray 0xff commands that occur when deselecting the SD
|
|
* card.
|
|
*/
|
|
bus = qdev_get_child_bus(dev, "ssi");
|
|
|
|
sddev = ssi_create_slave(bus, "ssi-sd");
|
|
ssddev = ssi_create_slave(bus, "ssd0323");
|
|
gpio_out[GPIO_D][0] = qemu_irq_split(qdev_get_gpio_in(sddev, 0),
|
|
qdev_get_gpio_in(ssddev, 0));
|
|
gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 1);
|
|
|
|
/* Make sure the select pin is high. */
|
|
qemu_irq_raise(gpio_out[GPIO_D][0]);
|
|
}
|
|
}
|
|
if (board->dc4 & (1 << 28)) {
|
|
DeviceState *enet;
|
|
|
|
qemu_check_nic_model(&nd_table[0], "stellaris");
|
|
|
|
enet = qdev_create(NULL, "stellaris_enet");
|
|
qdev_set_nic_properties(enet, &nd_table[0]);
|
|
qdev_init_nofail(enet);
|
|
sysbus_mmio_map(sysbus_from_qdev(enet), 0, 0x40048000);
|
|
sysbus_connect_irq(sysbus_from_qdev(enet), 0, pic[42]);
|
|
}
|
|
if (board->peripherals & BP_GAMEPAD) {
|
|
qemu_irq gpad_irq[5];
|
|
static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
|
|
|
|
gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
|
|
gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
|
|
gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
|
|
gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
|
|
gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
|
|
|
|
stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
|
|
}
|
|
for (i = 0; i < 7; i++) {
|
|
if (board->dc4 & (1 << i)) {
|
|
for (j = 0; j < 8; j++) {
|
|
if (gpio_out[i][j]) {
|
|
qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* FIXME: Figure out how to generate these from stellaris_boards. */
|
|
static void lm3s811evb_init(QEMUMachineInitArgs *args)
|
|
{
|
|
const char *cpu_model = args->cpu_model;
|
|
const char *kernel_filename = args->kernel_filename;
|
|
stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
|
|
}
|
|
|
|
static void lm3s6965evb_init(QEMUMachineInitArgs *args)
|
|
{
|
|
const char *cpu_model = args->cpu_model;
|
|
const char *kernel_filename = args->kernel_filename;
|
|
stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
|
|
}
|
|
|
|
static QEMUMachine lm3s811evb_machine = {
|
|
.name = "lm3s811evb",
|
|
.desc = "Stellaris LM3S811EVB",
|
|
.init = lm3s811evb_init,
|
|
};
|
|
|
|
static QEMUMachine lm3s6965evb_machine = {
|
|
.name = "lm3s6965evb",
|
|
.desc = "Stellaris LM3S6965EVB",
|
|
.init = lm3s6965evb_init,
|
|
};
|
|
|
|
static void stellaris_machine_init(void)
|
|
{
|
|
qemu_register_machine(&lm3s811evb_machine);
|
|
qemu_register_machine(&lm3s6965evb_machine);
|
|
}
|
|
|
|
machine_init(stellaris_machine_init);
|
|
|
|
static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
sdc->init = stellaris_i2c_init;
|
|
}
|
|
|
|
static const TypeInfo stellaris_i2c_info = {
|
|
.name = "stellaris-i2c",
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(stellaris_i2c_state),
|
|
.class_init = stellaris_i2c_class_init,
|
|
};
|
|
|
|
static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
sdc->init = stellaris_gptm_init;
|
|
}
|
|
|
|
static const TypeInfo stellaris_gptm_info = {
|
|
.name = "stellaris-gptm",
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(gptm_state),
|
|
.class_init = stellaris_gptm_class_init,
|
|
};
|
|
|
|
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
sdc->init = stellaris_adc_init;
|
|
}
|
|
|
|
static const TypeInfo stellaris_adc_info = {
|
|
.name = "stellaris-adc",
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(stellaris_adc_state),
|
|
.class_init = stellaris_adc_class_init,
|
|
};
|
|
|
|
static void stellaris_register_types(void)
|
|
{
|
|
type_register_static(&stellaris_i2c_info);
|
|
type_register_static(&stellaris_gptm_info);
|
|
type_register_static(&stellaris_adc_info);
|
|
}
|
|
|
|
type_init(stellaris_register_types)
|