db1015e92e
Some typedefs and macros are defined after the type check macros.
This makes it difficult to automatically replace their
definitions with OBJECT_DECLARE_TYPE.
Patch generated using:
$ ./scripts/codeconverter/converter.py -i \
--pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')
which will split "typdef struct { ... } TypedefName"
declarations.
Followed by:
$ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \
$(git grep -l '' -- '*.[ch]')
which will:
- move the typedefs and #defines above the type check macros
- add missing #include "qom/object.h" lines if necessary
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-9-ehabkost@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-10-ehabkost@redhat.com>
Message-Id: <20200831210740.126168-11-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
126 lines
4.4 KiB
C
126 lines
4.4 KiB
C
/*
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* IOAPIC emulation logic - internal interfaces
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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* Copyright (c) 2009 Xiantao Zhang, Intel
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* Copyright (c) 2011 Jan Kiszka, Siemens AG
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_IOAPIC_INTERNAL_H
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#define QEMU_IOAPIC_INTERNAL_H
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#include "exec/memory.h"
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#include "hw/sysbus.h"
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#include "qemu/notify.h"
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#include "qom/object.h"
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#define MAX_IOAPICS 1
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#define IOAPIC_LVT_DEST_SHIFT 56
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#define IOAPIC_LVT_DEST_IDX_SHIFT 48
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#define IOAPIC_LVT_MASKED_SHIFT 16
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#define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15
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#define IOAPIC_LVT_REMOTE_IRR_SHIFT 14
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#define IOAPIC_LVT_POLARITY_SHIFT 13
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#define IOAPIC_LVT_DELIV_STATUS_SHIFT 12
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#define IOAPIC_LVT_DEST_MODE_SHIFT 11
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#define IOAPIC_LVT_DELIV_MODE_SHIFT 8
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#define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT)
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#define IOAPIC_LVT_TRIGGER_MODE (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT)
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#define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
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#define IOAPIC_LVT_POLARITY (1 << IOAPIC_LVT_POLARITY_SHIFT)
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#define IOAPIC_LVT_DELIV_STATUS (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT)
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#define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
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#define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
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/* Bits that are read-only for IOAPIC entry */
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#define IOAPIC_RO_BITS (IOAPIC_LVT_REMOTE_IRR | \
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IOAPIC_LVT_DELIV_STATUS)
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#define IOAPIC_RW_BITS (~(uint64_t)IOAPIC_RO_BITS)
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#define IOAPIC_TRIGGER_EDGE 0
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#define IOAPIC_TRIGGER_LEVEL 1
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/*io{apic,sapic} delivery mode*/
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#define IOAPIC_DM_FIXED 0x0
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#define IOAPIC_DM_LOWEST_PRIORITY 0x1
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#define IOAPIC_DM_PMI 0x2
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#define IOAPIC_DM_NMI 0x4
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#define IOAPIC_DM_INIT 0x5
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#define IOAPIC_DM_SIPI 0x6
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#define IOAPIC_DM_EXTINT 0x7
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#define IOAPIC_DM_MASK 0x7
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#define IOAPIC_VECTOR_MASK 0xff
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#define IOAPIC_IOREGSEL 0x00
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#define IOAPIC_IOWIN 0x10
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#define IOAPIC_EOI 0x40
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#define IOAPIC_REG_ID 0x00
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#define IOAPIC_REG_VER 0x01
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#define IOAPIC_REG_ARB 0x02
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#define IOAPIC_REG_REDTBL_BASE 0x10
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#define IOAPIC_ID 0x00
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#define IOAPIC_ID_SHIFT 24
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#define IOAPIC_ID_MASK 0xf
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#define IOAPIC_VER_ENTRIES_SHIFT 16
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typedef struct IOAPICCommonState IOAPICCommonState;
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#define TYPE_IOAPIC_COMMON "ioapic-common"
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typedef struct IOAPICCommonClass IOAPICCommonClass;
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#define IOAPIC_COMMON(obj) \
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OBJECT_CHECK(IOAPICCommonState, (obj), TYPE_IOAPIC_COMMON)
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#define IOAPIC_COMMON_CLASS(klass) \
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OBJECT_CLASS_CHECK(IOAPICCommonClass, (klass), TYPE_IOAPIC_COMMON)
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#define IOAPIC_COMMON_GET_CLASS(obj) \
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OBJECT_GET_CLASS(IOAPICCommonClass, (obj), TYPE_IOAPIC_COMMON)
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struct IOAPICCommonClass {
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SysBusDeviceClass parent_class;
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DeviceRealize realize;
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DeviceUnrealize unrealize;
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void (*pre_save)(IOAPICCommonState *s);
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void (*post_load)(IOAPICCommonState *s);
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};
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struct IOAPICCommonState {
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SysBusDevice busdev;
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MemoryRegion io_memory;
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uint8_t id;
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uint8_t ioregsel;
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uint32_t irr;
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uint64_t ioredtbl[IOAPIC_NUM_PINS];
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Notifier machine_done;
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uint8_t version;
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uint64_t irq_count[IOAPIC_NUM_PINS];
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int irq_level[IOAPIC_NUM_PINS];
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int irq_eoi[IOAPIC_NUM_PINS];
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QEMUTimer *delayed_ioapic_service_timer;
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};
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void ioapic_reset_common(DeviceState *dev);
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void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s);
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void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level);
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#endif /* QEMU_IOAPIC_INTERNAL_H */
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