Richard Henderson db23e5d981 target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl ... Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-10-22 07:47:51 +10:00
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insn_trans	target/riscv: Fix orc.b implementation	2021-10-22 07:47:51 +10:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
bitmanip_helper.c	target/riscv: Add rev8 instruction, removing grev/grevi	2021-10-07 08:41:33 +10:00
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
cpu.h	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
cpu_bits.h	target/riscv: Create RISCVMXL enumeration	2021-10-22 07:47:51 +10:00
cpu_helper.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
csr.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
fpu_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
gdbstub.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
helper.h	target/riscv: Add rev8 instruction, removing grev/grevi	2021-10-07 08:41:33 +10:00
insn16.decode	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
insn32.decode	target/riscv: Remove RVB (replaced by Zb[abcs])	2021-10-07 08:41:33 +10:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
internals.h	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
machine.c	target/riscv: Split misa.mxl and misa.ext	2021-10-22 07:47:51 +10:00
meson.build	target/riscv: rvb: generalized reverse	2021-06-08 09:59:45 +10:00
monitor.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
op_helper.c	target/riscv: Reorg csr instructions	2021-09-01 11:59:12 +10:00
pmp.c	target/riscv: pmp: Fix some typos	2021-07-15 08:56:00 +10:00
pmp.h	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Split misa.mxl and misa.ext	2021-10-22 07:47:51 +10:00
vector_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00