fbd2e60ef1
Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux) and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx, stfdux) from legacy system to decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211029202424.175401-4-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
151 lines
5.9 KiB
Plaintext
151 lines
5.9 KiB
Plaintext
#
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# Power ISA decode for 32-bit insns (opcode space 0)
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#
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# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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&D rt ra si:int64_t
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@D ...... rt:5 ra:5 si:s16 &D
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&D_bf bf l:bool ra imm
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@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf
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@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf
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%ds_si 2:s14 !function=times_4
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@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
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&DX rt d
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%dx_d 6:s10 16:5 0:1
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@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
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&VX vrt vra vrb
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@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
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&X rt ra rb
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@X ...... rt:5 ra:5 rb:5 .......... . &X
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&X_bi rt bi
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@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
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&X_bfl bf l:bool ra rb
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@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
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### Fixed-Point Load Instructions
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LBZ 100010 ..... ..... ................ @D
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LBZU 100011 ..... ..... ................ @D
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LBZX 011111 ..... ..... ..... 0001010111 - @X
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LBZUX 011111 ..... ..... ..... 0001110111 - @X
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LHZ 101000 ..... ..... ................ @D
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LHZU 101001 ..... ..... ................ @D
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LHZX 011111 ..... ..... ..... 0100010111 - @X
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LHZUX 011111 ..... ..... ..... 0100110111 - @X
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LHA 101010 ..... ..... ................ @D
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LHAU 101011 ..... ..... ................ @D
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LHAX 011111 ..... ..... ..... 0101010111 - @X
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LHAXU 011111 ..... ..... ..... 0101110111 - @X
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LWZ 100000 ..... ..... ................ @D
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LWZU 100001 ..... ..... ................ @D
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LWZX 011111 ..... ..... ..... 0000010111 - @X
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LWZUX 011111 ..... ..... ..... 0000110111 - @X
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LWA 111010 ..... ..... ..............10 @DS
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LWAX 011111 ..... ..... ..... 0101010101 - @X
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LWAUX 011111 ..... ..... ..... 0101110101 - @X
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LD 111010 ..... ..... ..............00 @DS
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LDU 111010 ..... ..... ..............01 @DS
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LDX 011111 ..... ..... ..... 0000010101 - @X
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LDUX 011111 ..... ..... ..... 0000110101 - @X
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### Fixed-Point Store Instructions
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STB 100110 ..... ..... ................ @D
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STBU 100111 ..... ..... ................ @D
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STBX 011111 ..... ..... ..... 0011010111 - @X
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STBUX 011111 ..... ..... ..... 0011110111 - @X
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STH 101100 ..... ..... ................ @D
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STHU 101101 ..... ..... ................ @D
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STHX 011111 ..... ..... ..... 0110010111 - @X
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STHUX 011111 ..... ..... ..... 0110110111 - @X
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STW 100100 ..... ..... ................ @D
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STWU 100101 ..... ..... ................ @D
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STWX 011111 ..... ..... ..... 0010010111 - @X
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STWUX 011111 ..... ..... ..... 0010110111 - @X
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STD 111110 ..... ..... ..............00 @DS
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STDU 111110 ..... ..... ..............01 @DS
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STDX 011111 ..... ..... ..... 0010010101 - @X
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STDUX 011111 ..... ..... ..... 0010110101 - @X
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### Fixed-Point Compare Instructions
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CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
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CMPL 011111 ... - . ..... ..... 0000100000 - @X_bfl
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CMPI 001011 ... - . ..... ................ @D_bfs
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CMPLI 001010 ... - . ..... ................ @D_bfu
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### Fixed-Point Arithmetic Instructions
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ADDI 001110 ..... ..... ................ @D
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ADDIS 001111 ..... ..... ................ @D
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ADDPCIS 010011 ..... ..... .......... 00010 . @DX
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## Fixed-Point Logical Instructions
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CFUGED 011111 ..... ..... ..... 0011011100 - @X
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### Float-Point Load Instructions
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LFS 110000 ..... ..... ................ @D
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LFSU 110001 ..... ..... ................ @D
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LFSX 011111 ..... ..... ..... 1000010111 - @X
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LFSUX 011111 ..... ..... ..... 1000110111 - @X
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LFD 110010 ..... ..... ................ @D
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LFDU 110011 ..... ..... ................ @D
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LFDX 011111 ..... ..... ..... 1001010111 - @X
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LFDUX 011111 ..... ..... ..... 1001110111 - @X
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### Float-Point Store Instructions
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STFS 110100 ..... ...... ............... @D
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STFSU 110101 ..... ...... ............... @D
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STFSX 011111 ..... ...... .... 1010010111 - @X
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STFSUX 011111 ..... ...... .... 1010110111 - @X
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STFD 110110 ..... ...... ............... @D
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STFDU 110111 ..... ...... ............... @D
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STFDX 011111 ..... ...... .... 1011010111 - @X
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STFDUX 011111 ..... ...... .... 1011110111 - @X
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### Move To/From System Register Instructions
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SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
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SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
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SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
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SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
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## Vector Bit Manipulation Instruction
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VCFUGED 000100 ..... ..... ..... 10101001101 @VX
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