This will ease the definition of the new controllers for the AST2500 SoC and also ease the support of the segment registers, which provide a way to reconfigure the mapping window of each slave. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
254 lines
8.8 KiB
C
254 lines
8.8 KiB
C
/*
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* ASPEED SoC family
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*
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* Andrew Jeffery <andrew@aj.id.au>
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* Jeremy Kerr <jk@ozlabs.org>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/address-spaces.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/char/serial.h"
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#include "qemu/log.h"
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#include "hw/i2c/aspeed_i2c.h"
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#define ASPEED_SOC_UART_5_BASE 0x00184000
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#define ASPEED_SOC_IOMEM_SIZE 0x00200000
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#define ASPEED_SOC_IOMEM_BASE 0x1E600000
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#define ASPEED_SOC_FMC_BASE 0x1E620000
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#define ASPEED_SOC_SPI_BASE 0x1E630000
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#define ASPEED_SOC_VIC_BASE 0x1E6C0000
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#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
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#define ASPEED_SOC_SCU_BASE 0x1E6E2000
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#define ASPEED_SOC_TIMER_BASE 0x1E782000
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#define ASPEED_SOC_I2C_BASE 0x1E78A000
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static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
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static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
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#define AST2400_SDRAM_BASE 0x40000000
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#define AST2500_SDRAM_BASE 0x80000000
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static const AspeedSoCInfo aspeed_socs[] = {
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{ "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE },
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{ "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE },
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{ "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE },
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};
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/*
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* IO handlers: simply catch any reads/writes to IO addresses that aren't
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* handled by a device mapping.
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*/
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static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
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__func__, offset, size);
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return 0;
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}
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static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
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__func__, offset, value, size);
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}
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static const MemoryRegionOps aspeed_soc_io_ops = {
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.read = aspeed_soc_io_read,
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.write = aspeed_soc_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void aspeed_soc_init(Object *obj)
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{
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AspeedSoCState *s = ASPEED_SOC(obj);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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s->cpu = cpu_arm_init(sc->info->cpu_model);
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object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
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object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
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qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
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object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
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object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
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qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
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object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
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object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
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qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
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object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
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object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
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qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
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qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
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sc->info->silicon_rev);
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object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
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"hw-strap1", &error_abort);
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object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
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"hw-strap2", &error_abort);
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object_initialize(&s->fmc, sizeof(s->fmc), "aspeed.smc.fmc");
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object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
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qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
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object_initialize(&s->spi, sizeof(s->spi), "aspeed.smc.spi");
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object_property_add_child(obj, "spi", OBJECT(&s->spi), NULL);
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qdev_set_parent_bus(DEVICE(&s->spi), sysbus_get_default());
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object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
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object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
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qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
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qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
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sc->info->silicon_rev);
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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"ram-size", &error_abort);
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}
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static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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{
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int i;
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AspeedSoCState *s = ASPEED_SOC(dev);
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Error *err = NULL, *local_err = NULL;
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/* IO space */
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memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
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"aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
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memory_region_add_subregion_overlap(get_system_memory(),
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ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
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/* VIC */
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object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
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qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
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qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
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/* Timer */
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object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
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for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
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qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
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}
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/* SCU */
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object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
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/* UART - attach an 8250 to the IO space as our UART5 */
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if (serial_hds[0]) {
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qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
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serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
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uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
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}
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/* I2C */
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object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
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qdev_get_gpio_in(DEVICE(&s->vic), 12));
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/* FMC */
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object_property_set_int(OBJECT(&s->fmc), 1, "num-cs", &err);
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object_property_set_bool(OBJECT(&s->fmc), true, "realized", &local_err);
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error_propagate(&err, local_err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
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s->fmc.ctrl->flash_window_base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
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qdev_get_gpio_in(DEVICE(&s->vic), 19));
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/* SPI */
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object_property_set_int(OBJECT(&s->spi), 1, "num-cs", &err);
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object_property_set_bool(OBJECT(&s->spi), true, "realized", &local_err);
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error_propagate(&err, local_err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, ASPEED_SOC_SPI_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1,
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s->spi.ctrl->flash_window_base);
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/* SDMC - SDRAM Memory Controller */
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object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
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}
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static void aspeed_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
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sc->info = (AspeedSoCInfo *) data;
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dc->realize = aspeed_soc_realize;
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/*
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* Reason: creates an ARM CPU, thus use after free(), see
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* arm_cpu_class_init()
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*/
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dc->cannot_destroy_with_object_finalize_yet = true;
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}
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static const TypeInfo aspeed_soc_type_info = {
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.name = TYPE_ASPEED_SOC,
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.parent = TYPE_DEVICE,
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.instance_init = aspeed_soc_init,
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.instance_size = sizeof(AspeedSoCState),
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.class_size = sizeof(AspeedSoCClass),
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.abstract = true,
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};
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static void aspeed_soc_register_types(void)
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{
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int i;
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type_register_static(&aspeed_soc_type_info);
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for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
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TypeInfo ti = {
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.name = aspeed_socs[i].name,
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.parent = TYPE_ASPEED_SOC,
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.class_init = aspeed_soc_class_init,
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.class_data = (void *) &aspeed_socs[i],
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};
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type_register(&ti);
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}
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}
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type_init(aspeed_soc_register_types)
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