Commit6daf194d
,be62a2eb
and312fd5f
got rid of a bunch, but they keep coming back. Tracked down with the Coccinelle semantic patch from commit312fd5f
. Cc: Fam Zheng <famz@redhat.com> Cc: Peter Crosthwaite <crosthwaitepeter@gmail.com> Cc: Bharata B Rao <bharata@linux.vnet.ibm.com> Cc: Dominik Dingel <dingel@linux.vnet.ibm.com> Cc: David Hildenbrand <dahi@linux.vnet.ibm.com> Cc: Jason J. Herne <jjherne@linux.vnet.ibm.com> Cc: Stefan Berger <stefanb@linux.vnet.ibm.com> Cc: Dr. David Alan Gilbert <dgilbert@redhat.com> Cc: Changchun Ouyang <changchun.ouyang@intel.com> Cc: zhanghailiang <zhang.zhanghailiang@huawei.com> Cc: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Markus Armbruster <armbru@pond.sub.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Acked-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Acked-by: Fam Zheng <famz@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <1450452927-8346-17-git-send-email-armbru@redhat.com>
1484 lines
46 KiB
C
1484 lines
46 KiB
C
/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "cpu.h"
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#include "internals.h"
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#include "qemu-common.h"
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#include "hw/qdev-properties.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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#include "hw/arm/arm.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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static void arm_cpu_set_pc(CPUState *cs, vaddr value)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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cpu->env.regs[15] = value;
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}
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static bool arm_cpu_has_work(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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return !cpu->powered_off
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&& cs->interrupt_request &
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(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
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| CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
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| CPU_INTERRUPT_EXITTB);
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}
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static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
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{
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/* Reset a single ARMCPRegInfo register */
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ARMCPRegInfo *ri = value;
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ARMCPU *cpu = opaque;
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if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
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return;
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}
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if (ri->resetfn) {
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ri->resetfn(&cpu->env, ri);
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return;
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}
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/* A zero offset is never possible as it would be regs[0]
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* so we use it to indicate that reset is being handled elsewhere.
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* This is basically only used for fields in non-core coprocessors
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* (like the pxa2xx ones).
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*/
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if (!ri->fieldoffset) {
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return;
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}
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if (cpreg_field_is_64bit(ri)) {
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CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
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} else {
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CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
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}
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}
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static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
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{
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/* Purely an assertion check: we've already done reset once,
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* so now check that running the reset for the cpreg doesn't
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* change its value. This traps bugs where two different cpregs
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* both try to reset the same state field but to different values.
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*/
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ARMCPRegInfo *ri = value;
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ARMCPU *cpu = opaque;
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uint64_t oldvalue, newvalue;
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if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
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return;
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}
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oldvalue = read_raw_cp_reg(&cpu->env, ri);
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cp_reg_reset(key, value, opaque);
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newvalue = read_raw_cp_reg(&cpu->env, ri);
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assert(oldvalue == newvalue);
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}
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/* CPUClass::reset() */
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static void arm_cpu_reset(CPUState *s)
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{
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ARMCPU *cpu = ARM_CPU(s);
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
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CPUARMState *env = &cpu->env;
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acc->parent_reset(s);
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memset(env, 0, offsetof(CPUARMState, features));
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
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g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
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cpu->powered_off = cpu->start_powered_off;
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s->halted = cpu->start_powered_off;
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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}
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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/* 64 bit CPUs always start in 64 bit mode */
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env->aarch64 = 1;
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#if defined(CONFIG_USER_ONLY)
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env->pstate = PSTATE_MODE_EL0t;
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/* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
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env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
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/* and to the FP/Neon instructions */
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env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
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#else
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/* Reset into the highest available EL */
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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env->pstate = PSTATE_MODE_EL3h;
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} else if (arm_feature(env, ARM_FEATURE_EL2)) {
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env->pstate = PSTATE_MODE_EL2h;
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} else {
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env->pstate = PSTATE_MODE_EL1h;
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}
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env->pc = cpu->rvbar;
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#endif
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} else {
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#if defined(CONFIG_USER_ONLY)
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/* Userspace expects access to cp10 and cp11 for FP/Neon */
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env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
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#endif
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}
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#if defined(CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR;
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/* For user mode we must enable access to coprocessors */
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->cp15.c15_cpar = 3;
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} else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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env->cp15.c15_cpar = 1;
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}
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#else
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC;
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env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
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/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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* clear at reset. Initial SP and PC are loaded from ROM.
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*/
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if (IS_M(env)) {
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uint32_t initial_msp; /* Loaded from 0x0 */
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uint32_t initial_pc; /* Loaded from 0x4 */
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uint8_t *rom;
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env->daif &= ~PSTATE_I;
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rom = rom_ptr(0);
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if (rom) {
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/* Address zero is covered by ROM which hasn't yet been
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* copied into physical memory.
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*/
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initial_msp = ldl_p(rom);
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initial_pc = ldl_p(rom + 4);
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} else {
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/* Address zero not covered by a ROM blob, or the ROM blob
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* is in non-modifiable memory and this is a second reset after
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* it got copied into memory. In the latter case, rom_ptr
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* will return a NULL pointer and we should use ldl_phys instead.
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*/
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initial_msp = ldl_phys(s->as, 0);
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initial_pc = ldl_phys(s->as, 4);
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}
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env->regs[13] = initial_msp & 0xFFFFFFFC;
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env->regs[15] = initial_pc & ~1;
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env->thumb = initial_pc & 1;
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}
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/* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
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* executing as AArch32 then check if highvecs are enabled and
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* adjust the PC accordingly.
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*/
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if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
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env->regs[15] = 0xFFFF0000;
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}
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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#endif
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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set_default_nan_mode(1, &env->vfp.standard_fp_status);
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->vfp.fp_status);
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->vfp.standard_fp_status);
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tlb_flush(s, 1);
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#ifndef CONFIG_USER_ONLY
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if (kvm_enabled()) {
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kvm_arm_reset_vcpu(cpu);
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}
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#endif
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hw_breakpoint_update_all(cpu);
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hw_watchpoint_update_all(cpu);
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}
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bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUARMState *env = cs->env_ptr;
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uint32_t cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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uint32_t target_el;
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uint32_t excp_idx;
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bool ret = false;
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if (interrupt_request & CPU_INTERRUPT_FIQ) {
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excp_idx = EXCP_FIQ;
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target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
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if (arm_excp_unmasked(cs, excp_idx, target_el)) {
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cs->exception_index = excp_idx;
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env->exception.target_el = target_el;
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cc->do_interrupt(cs);
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ret = true;
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}
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}
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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excp_idx = EXCP_IRQ;
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target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
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if (arm_excp_unmasked(cs, excp_idx, target_el)) {
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cs->exception_index = excp_idx;
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env->exception.target_el = target_el;
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cc->do_interrupt(cs);
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ret = true;
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}
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}
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if (interrupt_request & CPU_INTERRUPT_VIRQ) {
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excp_idx = EXCP_VIRQ;
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target_el = 1;
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if (arm_excp_unmasked(cs, excp_idx, target_el)) {
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cs->exception_index = excp_idx;
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env->exception.target_el = target_el;
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cc->do_interrupt(cs);
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ret = true;
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}
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}
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if (interrupt_request & CPU_INTERRUPT_VFIQ) {
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excp_idx = EXCP_VFIQ;
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target_el = 1;
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if (arm_excp_unmasked(cs, excp_idx, target_el)) {
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cs->exception_index = excp_idx;
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env->exception.target_el = target_el;
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cc->do_interrupt(cs);
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ret = true;
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}
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}
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return ret;
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}
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#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
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static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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CPUClass *cc = CPU_GET_CLASS(cs);
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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bool ret = false;
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if (interrupt_request & CPU_INTERRUPT_FIQ
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&& !(env->daif & PSTATE_F)) {
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cs->exception_index = EXCP_FIQ;
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cc->do_interrupt(cs);
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ret = true;
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}
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/* ARMv7-M interrupt return works by loading a magic value
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* into the PC. On real hardware the load causes the
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* return to occur. The qemu implementation performs the
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* jump normally, then does the exception return when the
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* CPU tries to execute code at the magic address.
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* This will cause the magic PC value to be pushed to
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* the stack if an interrupt occurred at the wrong time.
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* We avoid this by disabling interrupts when
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* pc contains a magic address.
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*/
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if (interrupt_request & CPU_INTERRUPT_HARD
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&& !(env->daif & PSTATE_I)
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&& (env->regs[15] < 0xfffffff0)) {
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cs->exception_index = EXCP_IRQ;
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cc->do_interrupt(cs);
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ret = true;
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}
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return ret;
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}
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#endif
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#ifndef CONFIG_USER_ONLY
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static void arm_cpu_set_irq(void *opaque, int irq, int level)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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static const int mask[] = {
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[ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
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[ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
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[ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
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[ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
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};
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switch (irq) {
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case ARM_CPU_VIRQ:
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case ARM_CPU_VFIQ:
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assert(arm_feature(env, ARM_FEATURE_EL2));
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/* fall through */
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case ARM_CPU_IRQ:
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case ARM_CPU_FIQ:
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if (level) {
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cpu_interrupt(cs, mask[irq]);
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} else {
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cpu_reset_interrupt(cs, mask[irq]);
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}
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
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{
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#ifdef CONFIG_KVM
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ARMCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
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switch (irq) {
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case ARM_CPU_IRQ:
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kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
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break;
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case ARM_CPU_FIQ:
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kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
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break;
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default:
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g_assert_not_reached();
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}
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kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
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kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
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#endif
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}
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static bool arm_cpu_is_big_endian(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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int cur_el;
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cpu_synchronize_state(cs);
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/* In 32bit guest endianness is determined by looking at CPSR's E bit */
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if (!is_a64(env)) {
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return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
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}
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cur_el = arm_current_el(env);
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if (cur_el == 0) {
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return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
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}
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return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
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}
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#endif
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1ULL << feature;
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}
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static inline void unset_feature(CPUARMState *env, int feature)
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{
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env->features &= ~(1ULL << feature);
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}
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static int
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print_insn_thumb1(bfd_vma pc, disassemble_info *info)
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{
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return print_insn_arm(pc | 1, info);
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}
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static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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ARMCPU *ac = ARM_CPU(cpu);
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CPUARMState *env = &ac->env;
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if (is_a64(env)) {
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/* We might not be compiled with the A64 disassembler
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* because it needs a C++ compiler. Leave print_insn
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* unset in this case to use the caller default behaviour.
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*/
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#if defined(CONFIG_ARM_A64_DIS)
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info->print_insn = print_insn_arm_a64;
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#endif
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} else if (env->thumb) {
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info->print_insn = print_insn_thumb1;
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} else {
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info->print_insn = print_insn_arm;
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}
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if (env->bswap_code) {
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#ifdef TARGET_WORDS_BIGENDIAN
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info->endian = BFD_ENDIAN_LITTLE;
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#else
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info->endian = BFD_ENDIAN_BIG;
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#endif
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}
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}
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|
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#define ARM_CPUS_PER_CLUSTER 8
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|
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static void arm_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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ARMCPU *cpu = ARM_CPU(obj);
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static bool inited;
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uint32_t Aff1, Aff0;
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cs->env_ptr = &cpu->env;
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cpu_exec_init(cs, &error_abort);
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cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
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g_free, g_free);
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/* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
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* We don't support setting cluster ID ([16..23]) (known as Aff2
|
|
* in later ARM ARM versions), or any of the higher affinity level fields,
|
|
* so these bits always RAZ.
|
|
*/
|
|
Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
|
|
Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
|
|
cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
/* Our inbound IRQ and FIQ lines */
|
|
if (kvm_enabled()) {
|
|
/* VIRQ and VFIQ are unused with KVM but we add them to maintain
|
|
* the same interface as non-KVM CPUs.
|
|
*/
|
|
qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
|
|
} else {
|
|
qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
|
|
}
|
|
|
|
cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
|
|
arm_gt_ptimer_cb, cpu);
|
|
cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
|
|
arm_gt_vtimer_cb, cpu);
|
|
cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
|
|
arm_gt_htimer_cb, cpu);
|
|
cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
|
|
arm_gt_stimer_cb, cpu);
|
|
qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
|
|
ARRAY_SIZE(cpu->gt_timer_outputs));
|
|
#endif
|
|
|
|
/* DTB consumers generally don't in fact care what the 'compatible'
|
|
* string is, so always provide some string and trust that a hypothetical
|
|
* picky DTB consumer will also provide a helpful error message.
|
|
*/
|
|
cpu->dtb_compatible = "qemu,unknown";
|
|
cpu->psci_version = 1; /* By default assume PSCI v0.1 */
|
|
cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
|
|
|
|
if (tcg_enabled()) {
|
|
cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
|
|
if (!inited) {
|
|
inited = true;
|
|
arm_translate_init();
|
|
}
|
|
}
|
|
}
|
|
|
|
static Property arm_cpu_reset_cbar_property =
|
|
DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
|
|
|
|
static Property arm_cpu_reset_hivecs_property =
|
|
DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
|
|
|
|
static Property arm_cpu_rvbar_property =
|
|
DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
|
|
|
|
static Property arm_cpu_has_el3_property =
|
|
DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
|
|
|
|
static Property arm_cpu_has_mpu_property =
|
|
DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
|
|
|
|
static Property arm_cpu_pmsav7_dregion_property =
|
|
DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
|
|
|
|
static void arm_cpu_post_init(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
|
|
arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
|
|
qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
|
|
&error_abort);
|
|
}
|
|
|
|
if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
|
|
qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
|
|
&error_abort);
|
|
}
|
|
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
|
|
qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
|
|
&error_abort);
|
|
}
|
|
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
|
|
/* Add the has_el3 state CPU property only if EL3 is allowed. This will
|
|
* prevent "has_el3" from existing on CPUs which cannot support EL3.
|
|
*/
|
|
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
|
|
&error_abort);
|
|
}
|
|
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
|
|
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
|
|
&error_abort);
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
|
|
qdev_property_add_static(DEVICE(obj),
|
|
&arm_cpu_pmsav7_dregion_property,
|
|
&error_abort);
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
static void arm_cpu_finalizefn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
g_hash_table_destroy(cpu->cp_regs);
|
|
}
|
|
|
|
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
|
|
{
|
|
CPUState *cs = CPU(dev);
|
|
ARMCPU *cpu = ARM_CPU(dev);
|
|
ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
/* Some features automatically imply others: */
|
|
if (arm_feature(env, ARM_FEATURE_V8)) {
|
|
set_feature(env, ARM_FEATURE_V7);
|
|
set_feature(env, ARM_FEATURE_ARM_DIV);
|
|
set_feature(env, ARM_FEATURE_LPAE);
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_V7)) {
|
|
set_feature(env, ARM_FEATURE_VAPA);
|
|
set_feature(env, ARM_FEATURE_THUMB2);
|
|
set_feature(env, ARM_FEATURE_MPIDR);
|
|
if (!arm_feature(env, ARM_FEATURE_M)) {
|
|
set_feature(env, ARM_FEATURE_V6K);
|
|
} else {
|
|
set_feature(env, ARM_FEATURE_V6);
|
|
}
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_V6K)) {
|
|
set_feature(env, ARM_FEATURE_V6);
|
|
set_feature(env, ARM_FEATURE_MVFR);
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_V6)) {
|
|
set_feature(env, ARM_FEATURE_V5);
|
|
if (!arm_feature(env, ARM_FEATURE_M)) {
|
|
set_feature(env, ARM_FEATURE_AUXCR);
|
|
}
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_V5)) {
|
|
set_feature(env, ARM_FEATURE_V4T);
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_M)) {
|
|
set_feature(env, ARM_FEATURE_THUMB_DIV);
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
|
|
set_feature(env, ARM_FEATURE_THUMB_DIV);
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_VFP4)) {
|
|
set_feature(env, ARM_FEATURE_VFP3);
|
|
set_feature(env, ARM_FEATURE_VFP_FP16);
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_VFP3)) {
|
|
set_feature(env, ARM_FEATURE_VFP);
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_LPAE)) {
|
|
set_feature(env, ARM_FEATURE_V7MP);
|
|
set_feature(env, ARM_FEATURE_PXN);
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
|
|
set_feature(env, ARM_FEATURE_CBAR);
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_THUMB2) &&
|
|
!arm_feature(env, ARM_FEATURE_M)) {
|
|
set_feature(env, ARM_FEATURE_THUMB_DSP);
|
|
}
|
|
|
|
if (cpu->reset_hivecs) {
|
|
cpu->reset_sctlr |= (1 << 13);
|
|
}
|
|
|
|
if (!cpu->has_el3) {
|
|
/* If the has_el3 CPU property is disabled then we need to disable the
|
|
* feature.
|
|
*/
|
|
unset_feature(env, ARM_FEATURE_EL3);
|
|
|
|
/* Disable the security extension feature bits in the processor feature
|
|
* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
|
|
*/
|
|
cpu->id_pfr1 &= ~0xf0;
|
|
cpu->id_aa64pfr0 &= ~0xf000;
|
|
}
|
|
|
|
if (!cpu->has_mpu) {
|
|
unset_feature(env, ARM_FEATURE_MPU);
|
|
}
|
|
|
|
if (arm_feature(env, ARM_FEATURE_MPU) &&
|
|
arm_feature(env, ARM_FEATURE_V7)) {
|
|
uint32_t nr = cpu->pmsav7_dregion;
|
|
|
|
if (nr > 0xff) {
|
|
error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
|
|
return;
|
|
}
|
|
|
|
if (nr) {
|
|
env->pmsav7.drbar = g_new0(uint32_t, nr);
|
|
env->pmsav7.drsr = g_new0(uint32_t, nr);
|
|
env->pmsav7.dracr = g_new0(uint32_t, nr);
|
|
}
|
|
}
|
|
|
|
register_cp_regs_for_features(cpu);
|
|
arm_cpu_register_gdb_regs_for_features(cpu);
|
|
|
|
init_cpreg_list(cpu);
|
|
|
|
qemu_init_vcpu(cs);
|
|
cpu_reset(cs);
|
|
|
|
acc->parent_realize(dev, errp);
|
|
}
|
|
|
|
static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
|
|
{
|
|
ObjectClass *oc;
|
|
char *typename;
|
|
char **cpuname;
|
|
|
|
if (!cpu_model) {
|
|
return NULL;
|
|
}
|
|
|
|
cpuname = g_strsplit(cpu_model, ",", 1);
|
|
typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
|
|
oc = object_class_by_name(typename);
|
|
g_strfreev(cpuname);
|
|
g_free(typename);
|
|
if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
|
|
object_class_is_abstract(oc)) {
|
|
return NULL;
|
|
}
|
|
return oc;
|
|
}
|
|
|
|
/* CPU models. These are not needed for the AArch64 linux-user build. */
|
|
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
|
|
|
|
static void arm926_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,arm926";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
|
|
cpu->midr = 0x41069265;
|
|
cpu->reset_fpsid = 0x41011090;
|
|
cpu->ctr = 0x1dd20d2;
|
|
cpu->reset_sctlr = 0x00090078;
|
|
}
|
|
|
|
static void arm946_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,arm946";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_MPU);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
cpu->midr = 0x41059461;
|
|
cpu->ctr = 0x0f004006;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void arm1026_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,arm1026";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP);
|
|
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
|
|
cpu->midr = 0x4106a262;
|
|
cpu->reset_fpsid = 0x410110a0;
|
|
cpu->ctr = 0x1dd20d2;
|
|
cpu->reset_sctlr = 0x00090078;
|
|
cpu->reset_auxcr = 1;
|
|
{
|
|
/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
|
|
ARMCPRegInfo ifar = {
|
|
.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
|
|
.access = PL1_RW,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
|
|
.resetvalue = 0
|
|
};
|
|
define_one_arm_cp_reg(cpu, &ifar);
|
|
}
|
|
}
|
|
|
|
static void arm1136_r2_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
|
|
* older core than plain "arm1136". In particular this does not
|
|
* have the v6K features.
|
|
* These ID register values are correct for 1136 but may be wrong
|
|
* for 1136_r2 (in particular r0p2 does not actually implement most
|
|
* of the ID registers).
|
|
*/
|
|
|
|
cpu->dtb_compatible = "arm,arm1136";
|
|
set_feature(&cpu->env, ARM_FEATURE_V6);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
|
|
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
|
|
cpu->midr = 0x4107b362;
|
|
cpu->reset_fpsid = 0x410120b4;
|
|
cpu->mvfr0 = 0x11111111;
|
|
cpu->mvfr1 = 0x00000000;
|
|
cpu->ctr = 0x1dd20d2;
|
|
cpu->reset_sctlr = 0x00050078;
|
|
cpu->id_pfr0 = 0x111;
|
|
cpu->id_pfr1 = 0x1;
|
|
cpu->id_dfr0 = 0x2;
|
|
cpu->id_afr0 = 0x3;
|
|
cpu->id_mmfr0 = 0x01130003;
|
|
cpu->id_mmfr1 = 0x10030302;
|
|
cpu->id_mmfr2 = 0x01222110;
|
|
cpu->id_isar0 = 0x00140011;
|
|
cpu->id_isar1 = 0x12002111;
|
|
cpu->id_isar2 = 0x11231111;
|
|
cpu->id_isar3 = 0x01102131;
|
|
cpu->id_isar4 = 0x141;
|
|
cpu->reset_auxcr = 7;
|
|
}
|
|
|
|
static void arm1136_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,arm1136";
|
|
set_feature(&cpu->env, ARM_FEATURE_V6K);
|
|
set_feature(&cpu->env, ARM_FEATURE_V6);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
|
|
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
|
|
cpu->midr = 0x4117b363;
|
|
cpu->reset_fpsid = 0x410120b4;
|
|
cpu->mvfr0 = 0x11111111;
|
|
cpu->mvfr1 = 0x00000000;
|
|
cpu->ctr = 0x1dd20d2;
|
|
cpu->reset_sctlr = 0x00050078;
|
|
cpu->id_pfr0 = 0x111;
|
|
cpu->id_pfr1 = 0x1;
|
|
cpu->id_dfr0 = 0x2;
|
|
cpu->id_afr0 = 0x3;
|
|
cpu->id_mmfr0 = 0x01130003;
|
|
cpu->id_mmfr1 = 0x10030302;
|
|
cpu->id_mmfr2 = 0x01222110;
|
|
cpu->id_isar0 = 0x00140011;
|
|
cpu->id_isar1 = 0x12002111;
|
|
cpu->id_isar2 = 0x11231111;
|
|
cpu->id_isar3 = 0x01102131;
|
|
cpu->id_isar4 = 0x141;
|
|
cpu->reset_auxcr = 7;
|
|
}
|
|
|
|
static void arm1176_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,arm1176";
|
|
set_feature(&cpu->env, ARM_FEATURE_V6K);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP);
|
|
set_feature(&cpu->env, ARM_FEATURE_VAPA);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
|
|
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
|
|
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
|
cpu->midr = 0x410fb767;
|
|
cpu->reset_fpsid = 0x410120b5;
|
|
cpu->mvfr0 = 0x11111111;
|
|
cpu->mvfr1 = 0x00000000;
|
|
cpu->ctr = 0x1dd20d2;
|
|
cpu->reset_sctlr = 0x00050078;
|
|
cpu->id_pfr0 = 0x111;
|
|
cpu->id_pfr1 = 0x11;
|
|
cpu->id_dfr0 = 0x33;
|
|
cpu->id_afr0 = 0;
|
|
cpu->id_mmfr0 = 0x01130003;
|
|
cpu->id_mmfr1 = 0x10030302;
|
|
cpu->id_mmfr2 = 0x01222100;
|
|
cpu->id_isar0 = 0x0140011;
|
|
cpu->id_isar1 = 0x12002111;
|
|
cpu->id_isar2 = 0x11231121;
|
|
cpu->id_isar3 = 0x01102131;
|
|
cpu->id_isar4 = 0x01141;
|
|
cpu->reset_auxcr = 7;
|
|
}
|
|
|
|
static void arm11mpcore_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,arm11mpcore";
|
|
set_feature(&cpu->env, ARM_FEATURE_V6K);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP);
|
|
set_feature(&cpu->env, ARM_FEATURE_VAPA);
|
|
set_feature(&cpu->env, ARM_FEATURE_MPIDR);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
cpu->midr = 0x410fb022;
|
|
cpu->reset_fpsid = 0x410120b4;
|
|
cpu->mvfr0 = 0x11111111;
|
|
cpu->mvfr1 = 0x00000000;
|
|
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
|
|
cpu->id_pfr0 = 0x111;
|
|
cpu->id_pfr1 = 0x1;
|
|
cpu->id_dfr0 = 0;
|
|
cpu->id_afr0 = 0x2;
|
|
cpu->id_mmfr0 = 0x01100103;
|
|
cpu->id_mmfr1 = 0x10020302;
|
|
cpu->id_mmfr2 = 0x01222000;
|
|
cpu->id_isar0 = 0x00100011;
|
|
cpu->id_isar1 = 0x12002111;
|
|
cpu->id_isar2 = 0x11221011;
|
|
cpu->id_isar3 = 0x01102131;
|
|
cpu->id_isar4 = 0x141;
|
|
cpu->reset_auxcr = 1;
|
|
}
|
|
|
|
static void cortex_m3_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
set_feature(&cpu->env, ARM_FEATURE_V7);
|
|
set_feature(&cpu->env, ARM_FEATURE_M);
|
|
cpu->midr = 0x410fc231;
|
|
}
|
|
|
|
static void cortex_m4_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
set_feature(&cpu->env, ARM_FEATURE_V7);
|
|
set_feature(&cpu->env, ARM_FEATURE_M);
|
|
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
|
|
cpu->midr = 0x410fc240; /* r0p0 */
|
|
}
|
|
static void arm_v7m_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
|
|
#endif
|
|
|
|
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
|
|
}
|
|
|
|
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
|
|
/* Dummy the TCM region regs for the moment */
|
|
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
|
|
.access = PL1_RW, .type = ARM_CP_CONST },
|
|
{ .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
|
|
.access = PL1_RW, .type = ARM_CP_CONST },
|
|
REGINFO_SENTINEL
|
|
};
|
|
|
|
static void cortex_r5_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
set_feature(&cpu->env, ARM_FEATURE_V7);
|
|
set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
|
|
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
|
|
set_feature(&cpu->env, ARM_FEATURE_V7MP);
|
|
set_feature(&cpu->env, ARM_FEATURE_MPU);
|
|
cpu->midr = 0x411fc153; /* r1p3 */
|
|
cpu->id_pfr0 = 0x0131;
|
|
cpu->id_pfr1 = 0x001;
|
|
cpu->id_dfr0 = 0x010400;
|
|
cpu->id_afr0 = 0x0;
|
|
cpu->id_mmfr0 = 0x0210030;
|
|
cpu->id_mmfr1 = 0x00000000;
|
|
cpu->id_mmfr2 = 0x01200000;
|
|
cpu->id_mmfr3 = 0x0211;
|
|
cpu->id_isar0 = 0x2101111;
|
|
cpu->id_isar1 = 0x13112111;
|
|
cpu->id_isar2 = 0x21232141;
|
|
cpu->id_isar3 = 0x01112131;
|
|
cpu->id_isar4 = 0x0010142;
|
|
cpu->id_isar5 = 0x0;
|
|
cpu->mp_is_up = true;
|
|
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
|
|
}
|
|
|
|
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
|
|
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
|
|
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
|
{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
|
|
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
|
REGINFO_SENTINEL
|
|
};
|
|
|
|
static void cortex_a8_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,cortex-a8";
|
|
set_feature(&cpu->env, ARM_FEATURE_V7);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP3);
|
|
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
|
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
|
cpu->midr = 0x410fc080;
|
|
cpu->reset_fpsid = 0x410330c0;
|
|
cpu->mvfr0 = 0x11110222;
|
|
cpu->mvfr1 = 0x00011100;
|
|
cpu->ctr = 0x82048004;
|
|
cpu->reset_sctlr = 0x00c50078;
|
|
cpu->id_pfr0 = 0x1031;
|
|
cpu->id_pfr1 = 0x11;
|
|
cpu->id_dfr0 = 0x400;
|
|
cpu->id_afr0 = 0;
|
|
cpu->id_mmfr0 = 0x31100003;
|
|
cpu->id_mmfr1 = 0x20000000;
|
|
cpu->id_mmfr2 = 0x01202000;
|
|
cpu->id_mmfr3 = 0x11;
|
|
cpu->id_isar0 = 0x00101111;
|
|
cpu->id_isar1 = 0x12112111;
|
|
cpu->id_isar2 = 0x21232031;
|
|
cpu->id_isar3 = 0x11112131;
|
|
cpu->id_isar4 = 0x00111142;
|
|
cpu->dbgdidr = 0x15141000;
|
|
cpu->clidr = (1 << 27) | (2 << 24) | 3;
|
|
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
|
|
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
|
|
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
|
|
cpu->reset_auxcr = 2;
|
|
define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
|
|
}
|
|
|
|
static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
|
|
/* power_control should be set to maximum latency. Again,
|
|
* default to 0 and set by private hook
|
|
*/
|
|
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
|
|
.access = PL1_RW, .resetvalue = 0,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
|
|
{ .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
|
|
.access = PL1_RW, .resetvalue = 0,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
|
|
{ .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
|
|
.access = PL1_RW, .resetvalue = 0,
|
|
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
|
|
{ .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
|
|
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
|
/* TLB lockdown control */
|
|
{ .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
|
|
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
|
{ .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
|
|
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
|
{ .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
|
|
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
|
{ .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
|
|
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
|
{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
|
|
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
|
REGINFO_SENTINEL
|
|
};
|
|
|
|
static void cortex_a9_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,cortex-a9";
|
|
set_feature(&cpu->env, ARM_FEATURE_V7);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP3);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
|
|
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
|
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
|
|
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
|
/* Note that A9 supports the MP extensions even for
|
|
* A9UP and single-core A9MP (which are both different
|
|
* and valid configurations; we don't model A9UP).
|
|
*/
|
|
set_feature(&cpu->env, ARM_FEATURE_V7MP);
|
|
set_feature(&cpu->env, ARM_FEATURE_CBAR);
|
|
cpu->midr = 0x410fc090;
|
|
cpu->reset_fpsid = 0x41033090;
|
|
cpu->mvfr0 = 0x11110222;
|
|
cpu->mvfr1 = 0x01111111;
|
|
cpu->ctr = 0x80038003;
|
|
cpu->reset_sctlr = 0x00c50078;
|
|
cpu->id_pfr0 = 0x1031;
|
|
cpu->id_pfr1 = 0x11;
|
|
cpu->id_dfr0 = 0x000;
|
|
cpu->id_afr0 = 0;
|
|
cpu->id_mmfr0 = 0x00100103;
|
|
cpu->id_mmfr1 = 0x20000000;
|
|
cpu->id_mmfr2 = 0x01230000;
|
|
cpu->id_mmfr3 = 0x00002111;
|
|
cpu->id_isar0 = 0x00101111;
|
|
cpu->id_isar1 = 0x13112111;
|
|
cpu->id_isar2 = 0x21232041;
|
|
cpu->id_isar3 = 0x11112131;
|
|
cpu->id_isar4 = 0x00111142;
|
|
cpu->dbgdidr = 0x35141000;
|
|
cpu->clidr = (1 << 27) | (1 << 24) | 3;
|
|
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
|
|
cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
|
|
define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
|
|
}
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
|
|
{
|
|
/* Linux wants the number of processors from here.
|
|
* Might as well set the interrupt-controller bit too.
|
|
*/
|
|
return ((smp_cpus - 1) << 24) | (1 << 23);
|
|
}
|
|
#endif
|
|
|
|
static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
|
|
#ifndef CONFIG_USER_ONLY
|
|
{ .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
|
|
.access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
|
|
.writefn = arm_cp_write_ignore, },
|
|
#endif
|
|
{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
|
|
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
|
REGINFO_SENTINEL
|
|
};
|
|
|
|
static void cortex_a15_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,cortex-a15";
|
|
set_feature(&cpu->env, ARM_FEATURE_V7);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP4);
|
|
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
|
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
|
|
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
|
|
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
|
|
set_feature(&cpu->env, ARM_FEATURE_LPAE);
|
|
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
|
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
|
|
cpu->midr = 0x412fc0f1;
|
|
cpu->reset_fpsid = 0x410430f0;
|
|
cpu->mvfr0 = 0x10110222;
|
|
cpu->mvfr1 = 0x11111111;
|
|
cpu->ctr = 0x8444c004;
|
|
cpu->reset_sctlr = 0x00c50078;
|
|
cpu->id_pfr0 = 0x00001131;
|
|
cpu->id_pfr1 = 0x00011011;
|
|
cpu->id_dfr0 = 0x02010555;
|
|
cpu->id_afr0 = 0x00000000;
|
|
cpu->id_mmfr0 = 0x10201105;
|
|
cpu->id_mmfr1 = 0x20000000;
|
|
cpu->id_mmfr2 = 0x01240000;
|
|
cpu->id_mmfr3 = 0x02102211;
|
|
cpu->id_isar0 = 0x02101110;
|
|
cpu->id_isar1 = 0x13112111;
|
|
cpu->id_isar2 = 0x21232041;
|
|
cpu->id_isar3 = 0x11112131;
|
|
cpu->id_isar4 = 0x10011142;
|
|
cpu->dbgdidr = 0x3515f021;
|
|
cpu->clidr = 0x0a200023;
|
|
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
|
|
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
|
|
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
|
|
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
|
|
}
|
|
|
|
static void ti925t_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
set_feature(&cpu->env, ARM_FEATURE_V4T);
|
|
set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
|
|
cpu->midr = ARM_CPUID_TI925T;
|
|
cpu->ctr = 0x5109149;
|
|
cpu->reset_sctlr = 0x00000070;
|
|
}
|
|
|
|
static void sa1100_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "intel,sa1100";
|
|
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
cpu->midr = 0x4401A11B;
|
|
cpu->reset_sctlr = 0x00000070;
|
|
}
|
|
|
|
static void sa1110_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
|
|
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
|
|
cpu->midr = 0x6901B119;
|
|
cpu->reset_sctlr = 0x00000070;
|
|
}
|
|
|
|
static void pxa250_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
cpu->midr = 0x69052100;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void pxa255_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
cpu->midr = 0x69052d00;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void pxa260_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
cpu->midr = 0x69052903;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void pxa261_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
cpu->midr = 0x69052d05;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void pxa262_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
cpu->midr = 0x69052d06;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void pxa270a0_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
|
|
cpu->midr = 0x69054110;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void pxa270a1_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
|
|
cpu->midr = 0x69054111;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void pxa270b0_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
|
|
cpu->midr = 0x69054112;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void pxa270b1_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
|
|
cpu->midr = 0x69054113;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void pxa270c0_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
|
|
cpu->midr = 0x69054114;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
static void pxa270c5_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "marvell,xscale";
|
|
set_feature(&cpu->env, ARM_FEATURE_V5);
|
|
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
|
|
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
|
|
cpu->midr = 0x69054117;
|
|
cpu->ctr = 0xd172172;
|
|
cpu->reset_sctlr = 0x00000078;
|
|
}
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
static void arm_any_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
set_feature(&cpu->env, ARM_FEATURE_V8);
|
|
set_feature(&cpu->env, ARM_FEATURE_VFP4);
|
|
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
|
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
|
|
set_feature(&cpu->env, ARM_FEATURE_V8_AES);
|
|
set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
|
|
set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
|
|
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
|
|
set_feature(&cpu->env, ARM_FEATURE_CRC);
|
|
cpu->midr = 0xffffffff;
|
|
}
|
|
#endif
|
|
|
|
#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
|
|
|
|
typedef struct ARMCPUInfo {
|
|
const char *name;
|
|
void (*initfn)(Object *obj);
|
|
void (*class_init)(ObjectClass *oc, void *data);
|
|
} ARMCPUInfo;
|
|
|
|
static const ARMCPUInfo arm_cpus[] = {
|
|
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
|
|
{ .name = "arm926", .initfn = arm926_initfn },
|
|
{ .name = "arm946", .initfn = arm946_initfn },
|
|
{ .name = "arm1026", .initfn = arm1026_initfn },
|
|
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
|
|
* older core than plain "arm1136". In particular this does not
|
|
* have the v6K features.
|
|
*/
|
|
{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
|
|
{ .name = "arm1136", .initfn = arm1136_initfn },
|
|
{ .name = "arm1176", .initfn = arm1176_initfn },
|
|
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
|
|
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
|
|
.class_init = arm_v7m_class_init },
|
|
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
|
|
.class_init = arm_v7m_class_init },
|
|
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
|
|
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
|
|
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
|
|
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
|
|
{ .name = "ti925t", .initfn = ti925t_initfn },
|
|
{ .name = "sa1100", .initfn = sa1100_initfn },
|
|
{ .name = "sa1110", .initfn = sa1110_initfn },
|
|
{ .name = "pxa250", .initfn = pxa250_initfn },
|
|
{ .name = "pxa255", .initfn = pxa255_initfn },
|
|
{ .name = "pxa260", .initfn = pxa260_initfn },
|
|
{ .name = "pxa261", .initfn = pxa261_initfn },
|
|
{ .name = "pxa262", .initfn = pxa262_initfn },
|
|
/* "pxa270" is an alias for "pxa270-a0" */
|
|
{ .name = "pxa270", .initfn = pxa270a0_initfn },
|
|
{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
|
|
{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
|
|
{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
|
|
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
|
|
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
|
|
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
|
|
#ifdef CONFIG_USER_ONLY
|
|
{ .name = "any", .initfn = arm_any_initfn },
|
|
#endif
|
|
#endif
|
|
{ .name = NULL }
|
|
};
|
|
|
|
static Property arm_cpu_properties[] = {
|
|
DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
|
|
DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
|
|
DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
|
|
DEFINE_PROP_END_OF_LIST()
|
|
};
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
|
|
int mmu_idx)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
env->exception.vaddress = address;
|
|
if (rw == 2) {
|
|
cs->exception_index = EXCP_PREFETCH_ABORT;
|
|
} else {
|
|
cs->exception_index = EXCP_DATA_ABORT;
|
|
}
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
static void arm_cpu_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
|
|
CPUClass *cc = CPU_CLASS(acc);
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
acc->parent_realize = dc->realize;
|
|
dc->realize = arm_cpu_realizefn;
|
|
dc->props = arm_cpu_properties;
|
|
|
|
acc->parent_reset = cc->reset;
|
|
cc->reset = arm_cpu_reset;
|
|
|
|
cc->class_by_name = arm_cpu_class_by_name;
|
|
cc->has_work = arm_cpu_has_work;
|
|
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
|
|
cc->dump_state = arm_cpu_dump_state;
|
|
cc->set_pc = arm_cpu_set_pc;
|
|
cc->gdb_read_register = arm_cpu_gdb_read_register;
|
|
cc->gdb_write_register = arm_cpu_gdb_write_register;
|
|
#ifdef CONFIG_USER_ONLY
|
|
cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
|
|
#else
|
|
cc->do_interrupt = arm_cpu_do_interrupt;
|
|
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
|
|
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
|
|
cc->vmsd = &vmstate_arm_cpu;
|
|
cc->virtio_is_big_endian = arm_cpu_is_big_endian;
|
|
#endif
|
|
cc->gdb_num_core_regs = 26;
|
|
cc->gdb_core_xml_file = "arm-core.xml";
|
|
cc->gdb_stop_before_watchpoint = true;
|
|
cc->debug_excp_handler = arm_debug_excp_handler;
|
|
|
|
cc->disas_set_info = arm_disas_set_info;
|
|
|
|
/*
|
|
* Reason: arm_cpu_initfn() calls cpu_exec_init(), which saves
|
|
* the object in cpus -> dangling pointer after final
|
|
* object_unref().
|
|
*
|
|
* Once this is fixed, the devices that create ARM CPUs should be
|
|
* updated not to set cannot_destroy_with_object_finalize_yet,
|
|
* unless they still screw up something else.
|
|
*/
|
|
dc->cannot_destroy_with_object_finalize_yet = true;
|
|
}
|
|
|
|
static void cpu_register(const ARMCPUInfo *info)
|
|
{
|
|
TypeInfo type_info = {
|
|
.parent = TYPE_ARM_CPU,
|
|
.instance_size = sizeof(ARMCPU),
|
|
.instance_init = info->initfn,
|
|
.class_size = sizeof(ARMCPUClass),
|
|
.class_init = info->class_init,
|
|
};
|
|
|
|
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
|
|
type_register(&type_info);
|
|
g_free((void *)type_info.name);
|
|
}
|
|
|
|
static const TypeInfo arm_cpu_type_info = {
|
|
.name = TYPE_ARM_CPU,
|
|
.parent = TYPE_CPU,
|
|
.instance_size = sizeof(ARMCPU),
|
|
.instance_init = arm_cpu_initfn,
|
|
.instance_post_init = arm_cpu_post_init,
|
|
.instance_finalize = arm_cpu_finalizefn,
|
|
.abstract = true,
|
|
.class_size = sizeof(ARMCPUClass),
|
|
.class_init = arm_cpu_class_init,
|
|
};
|
|
|
|
static void arm_cpu_register_types(void)
|
|
{
|
|
const ARMCPUInfo *info = arm_cpus;
|
|
|
|
type_register_static(&arm_cpu_type_info);
|
|
|
|
while (info->name) {
|
|
cpu_register(info);
|
|
info++;
|
|
}
|
|
}
|
|
|
|
type_init(arm_cpu_register_types)
|