In icount mode, instructions that access io memory spaces in the middle of the translation block invoke TB recompilation. After recompilation, such instructions become last in the TB and are allowed to access io memory spaces. When the code includes instruction like i386 'xchg eax, 0xffffd080' which accesses APIC, QEMU goes into an infinite loop of the recompilation. This instruction includes two memory accesses - one read and one write. After the first access, APIC calls cpu_report_tpr_access, which restores the CPU state to get the current eip. But cpu_restore_state_from_tb resets the cpu->can_do_io flag which makes the second memory access invalid. Therefore the second memory access causes a recompilation of the block. Then these operations repeat again and again. This patch moves resetting cpu->can_do_io flag from cpu_restore_state_from_tb to cpu_loop_exit* functions. It also adds a parameter for cpu_restore_state which controls restoring icount. There is no need to restore icount when we only query CPU state without breaking the TB. Restoring it in such cases leads to the incorrect flow of the virtual time. In most cases new parameter is true (icount should be recalculated). But there are two cases in i386 and openrisc when the CPU state is only queried without the need to break the TB. This patch fixes both of these cases. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Message-Id: <20180409091320.12504.35329.stgit@pasha-VirtualBox> [rth: Make can_do_io setting unconditional; move from cpu_exec; make cpu_loop_exit_{noexc,restore} call cpu_loop_exit.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
499 lines
14 KiB
C
499 lines
14 KiB
C
/*
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* Alpha emulation cpu helpers for qemu.
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "fpu/softfloat.h"
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#include "exec/helper-proto.h"
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#define CONVERT_BIT(X, SRC, DST) \
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(SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
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uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env)
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{
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return (uint64_t)env->fpcr << 32;
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}
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void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
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{
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uint32_t fpcr = val >> 32;
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uint32_t t = 0;
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t |= CONVERT_BIT(fpcr, FPCR_INED, FPCR_INE);
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t |= CONVERT_BIT(fpcr, FPCR_UNFD, FPCR_UNF);
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t |= CONVERT_BIT(fpcr, FPCR_OVFD, FPCR_OVF);
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t |= CONVERT_BIT(fpcr, FPCR_DZED, FPCR_DZE);
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t |= CONVERT_BIT(fpcr, FPCR_INVD, FPCR_INV);
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env->fpcr = fpcr;
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env->fpcr_exc_enable = ~t & FPCR_STATUS_MASK;
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switch (fpcr & FPCR_DYN_MASK) {
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case FPCR_DYN_NORMAL:
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default:
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t = float_round_nearest_even;
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break;
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case FPCR_DYN_CHOPPED:
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t = float_round_to_zero;
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break;
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case FPCR_DYN_MINUS:
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t = float_round_down;
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break;
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case FPCR_DYN_PLUS:
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t = float_round_up;
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break;
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}
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env->fpcr_dyn_round = t;
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env->fpcr_flush_to_zero = (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ);
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env->fp_status.flush_inputs_to_zero = (fpcr & FPCR_DNZ) != 0;
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}
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uint64_t helper_load_fpcr(CPUAlphaState *env)
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{
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return cpu_alpha_load_fpcr(env);
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}
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void helper_store_fpcr(CPUAlphaState *env, uint64_t val)
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{
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cpu_alpha_store_fpcr(env, val);
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}
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static uint64_t *cpu_alpha_addr_gr(CPUAlphaState *env, unsigned reg)
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{
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#ifndef CONFIG_USER_ONLY
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if (env->flags & ENV_FLAG_PAL_MODE) {
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if (reg >= 8 && reg <= 14) {
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return &env->shadow[reg - 8];
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} else if (reg == 25) {
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return &env->shadow[7];
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}
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}
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#endif
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return &env->ir[reg];
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}
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uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg)
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{
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return *cpu_alpha_addr_gr(env, reg);
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}
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void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val)
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{
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*cpu_alpha_addr_gr(env, reg) = val;
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}
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#if defined(CONFIG_USER_ONLY)
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int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
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int rw, int mmu_idx)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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cs->exception_index = EXCP_MMFAULT;
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cpu->env.trap_arg0 = address;
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return 1;
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}
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#else
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/* Returns the OSF/1 entMM failure indication, or -1 on success. */
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static int get_physical_address(CPUAlphaState *env, target_ulong addr,
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int prot_need, int mmu_idx,
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target_ulong *pphys, int *pprot)
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{
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CPUState *cs = CPU(alpha_env_get_cpu(env));
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target_long saddr = addr;
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target_ulong phys = 0;
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target_ulong L1pte, L2pte, L3pte;
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target_ulong pt, index;
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int prot = 0;
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int ret = MM_K_ACV;
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/* Handle physical accesses. */
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if (mmu_idx == MMU_PHYS_IDX) {
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phys = addr;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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ret = -1;
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goto exit;
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}
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/* Ensure that the virtual address is properly sign-extended from
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the last implemented virtual address bit. */
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if (saddr >> TARGET_VIRT_ADDR_SPACE_BITS != saddr >> 63) {
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goto exit;
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}
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/* Translate the superpage. */
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/* ??? When we do more than emulate Unix PALcode, we'll need to
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determine which KSEG is actually active. */
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if (saddr < 0 && ((saddr >> 41) & 3) == 2) {
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/* User-space cannot access KSEG addresses. */
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if (mmu_idx != MMU_KERNEL_IDX) {
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goto exit;
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}
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/* For the benefit of the Typhoon chipset, move bit 40 to bit 43.
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We would not do this if the 48-bit KSEG is enabled. */
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phys = saddr & ((1ull << 40) - 1);
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phys |= (saddr & (1ull << 40)) << 3;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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ret = -1;
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goto exit;
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}
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/* Interpret the page table exactly like PALcode does. */
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pt = env->ptbr;
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/* TODO: rather than using ldq_phys() to read the page table we should
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* use address_space_ldq() so that we can handle the case when
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* the page table read gives a bus fault, rather than ignoring it.
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* For the existing code the zero data that ldq_phys will return for
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* an access to invalid memory will result in our treating the page
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* table as invalid, which may even be the right behaviour.
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*/
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/* L1 page table read. */
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index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff;
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L1pte = ldq_phys(cs->as, pt + index*8);
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if (unlikely((L1pte & PTE_VALID) == 0)) {
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ret = MM_K_TNV;
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goto exit;
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}
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if (unlikely((L1pte & PTE_KRE) == 0)) {
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goto exit;
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}
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pt = L1pte >> 32 << TARGET_PAGE_BITS;
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/* L2 page table read. */
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index = (addr >> (TARGET_PAGE_BITS + 10)) & 0x3ff;
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L2pte = ldq_phys(cs->as, pt + index*8);
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if (unlikely((L2pte & PTE_VALID) == 0)) {
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ret = MM_K_TNV;
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goto exit;
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}
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if (unlikely((L2pte & PTE_KRE) == 0)) {
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goto exit;
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}
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pt = L2pte >> 32 << TARGET_PAGE_BITS;
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/* L3 page table read. */
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index = (addr >> TARGET_PAGE_BITS) & 0x3ff;
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L3pte = ldq_phys(cs->as, pt + index*8);
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phys = L3pte >> 32 << TARGET_PAGE_BITS;
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if (unlikely((L3pte & PTE_VALID) == 0)) {
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ret = MM_K_TNV;
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goto exit;
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}
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#if PAGE_READ != 1 || PAGE_WRITE != 2 || PAGE_EXEC != 4
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# error page bits out of date
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#endif
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/* Check access violations. */
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if (L3pte & (PTE_KRE << mmu_idx)) {
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prot |= PAGE_READ | PAGE_EXEC;
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}
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if (L3pte & (PTE_KWE << mmu_idx)) {
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prot |= PAGE_WRITE;
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}
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if (unlikely((prot & prot_need) == 0 && prot_need)) {
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goto exit;
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}
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/* Check fault-on-operation violations. */
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prot &= ~(L3pte >> 1);
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ret = -1;
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if (unlikely((prot & prot_need) == 0)) {
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ret = (prot_need & PAGE_EXEC ? MM_K_FOE :
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prot_need & PAGE_WRITE ? MM_K_FOW :
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prot_need & PAGE_READ ? MM_K_FOR : -1);
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}
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exit:
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*pphys = phys;
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*pprot = prot;
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return ret;
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}
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hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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target_ulong phys;
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int prot, fail;
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fail = get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot);
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return (fail >= 0 ? -1 : phys);
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}
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int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, int rw,
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int mmu_idx)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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CPUAlphaState *env = &cpu->env;
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target_ulong phys;
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int prot, fail;
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fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot);
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if (unlikely(fail >= 0)) {
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cs->exception_index = EXCP_MMFAULT;
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env->trap_arg0 = addr;
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env->trap_arg1 = fail;
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env->trap_arg2 = (rw == 2 ? -1 : rw);
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return 1;
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}
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tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
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prot, mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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}
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#endif /* USER_ONLY */
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void alpha_cpu_do_interrupt(CPUState *cs)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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CPUAlphaState *env = &cpu->env;
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int i = cs->exception_index;
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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static int count;
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const char *name = "<unknown>";
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switch (i) {
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case EXCP_RESET:
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name = "reset";
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break;
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case EXCP_MCHK:
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name = "mchk";
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break;
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case EXCP_SMP_INTERRUPT:
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name = "smp_interrupt";
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break;
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case EXCP_CLK_INTERRUPT:
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name = "clk_interrupt";
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break;
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case EXCP_DEV_INTERRUPT:
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name = "dev_interrupt";
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break;
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case EXCP_MMFAULT:
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name = "mmfault";
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break;
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case EXCP_UNALIGN:
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name = "unalign";
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break;
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case EXCP_OPCDEC:
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name = "opcdec";
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break;
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case EXCP_ARITH:
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name = "arith";
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break;
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case EXCP_FEN:
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name = "fen";
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break;
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case EXCP_CALL_PAL:
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name = "call_pal";
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break;
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}
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qemu_log("INT %6d: %s(%#x) cpu=%d pc=%016"
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PRIx64 " sp=%016" PRIx64 "\n",
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++count, name, env->error_code, cs->cpu_index,
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env->pc, env->ir[IR_SP]);
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}
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cs->exception_index = -1;
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#if !defined(CONFIG_USER_ONLY)
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switch (i) {
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case EXCP_RESET:
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i = 0x0000;
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break;
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case EXCP_MCHK:
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i = 0x0080;
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break;
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case EXCP_SMP_INTERRUPT:
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i = 0x0100;
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break;
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case EXCP_CLK_INTERRUPT:
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i = 0x0180;
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break;
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case EXCP_DEV_INTERRUPT:
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i = 0x0200;
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break;
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case EXCP_MMFAULT:
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i = 0x0280;
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break;
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case EXCP_UNALIGN:
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i = 0x0300;
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break;
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case EXCP_OPCDEC:
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i = 0x0380;
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break;
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case EXCP_ARITH:
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i = 0x0400;
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break;
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case EXCP_FEN:
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i = 0x0480;
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break;
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case EXCP_CALL_PAL:
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i = env->error_code;
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/* There are 64 entry points for both privileged and unprivileged,
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with bit 0x80 indicating unprivileged. Each entry point gets
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64 bytes to do its job. */
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if (i & 0x80) {
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i = 0x2000 + (i - 0x80) * 64;
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} else {
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i = 0x1000 + i * 64;
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}
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break;
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default:
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cpu_abort(cs, "Unhandled CPU exception");
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}
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/* Remember where the exception happened. Emulate real hardware in
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that the low bit of the PC indicates PALmode. */
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env->exc_addr = env->pc | (env->flags & ENV_FLAG_PAL_MODE);
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/* Continue execution at the PALcode entry point. */
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env->pc = env->palbr + i;
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/* Switch to PALmode. */
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env->flags |= ENV_FLAG_PAL_MODE;
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#endif /* !USER_ONLY */
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}
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bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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CPUAlphaState *env = &cpu->env;
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int idx = -1;
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/* We never take interrupts while in PALmode. */
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if (env->flags & ENV_FLAG_PAL_MODE) {
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return false;
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}
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/* Fall through the switch, collecting the highest priority
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interrupt that isn't masked by the processor status IPL. */
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/* ??? This hard-codes the OSF/1 interrupt levels. */
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switch ((env->flags >> ENV_FLAG_PS_SHIFT) & PS_INT_MASK) {
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case 0 ... 3:
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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idx = EXCP_DEV_INTERRUPT;
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}
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/* FALLTHRU */
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case 4:
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if (interrupt_request & CPU_INTERRUPT_TIMER) {
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idx = EXCP_CLK_INTERRUPT;
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}
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/* FALLTHRU */
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case 5:
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if (interrupt_request & CPU_INTERRUPT_SMP) {
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idx = EXCP_SMP_INTERRUPT;
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}
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/* FALLTHRU */
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case 6:
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if (interrupt_request & CPU_INTERRUPT_MCHK) {
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idx = EXCP_MCHK;
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}
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}
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if (idx >= 0) {
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cs->exception_index = idx;
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env->error_code = 0;
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alpha_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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int flags)
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{
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static const char *linux_reg_names[] = {
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"v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ",
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"t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ",
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"a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ",
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"t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero",
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};
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AlphaCPU *cpu = ALPHA_CPU(cs);
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CPUAlphaState *env = &cpu->env;
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int i;
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cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n",
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env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8));
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for (i = 0; i < 31; i++) {
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cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,
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linux_reg_names[i], cpu_alpha_load_gr(env, i));
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if ((i % 3) == 2)
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cpu_fprintf(f, "\n");
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}
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cpu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n",
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env->lock_addr, env->lock_value);
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for (i = 0; i < 31; i++) {
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cpu_fprintf(f, "FIR%02d " TARGET_FMT_lx " ", i,
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*((uint64_t *)(&env->fir[i])));
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if ((i % 3) == 2)
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cpu_fprintf(f, "\n");
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}
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cpu_fprintf(f, "\n");
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}
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/* This should only be called from translate, via gen_excp.
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We expect that ENV->PC has already been updated. */
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void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
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{
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AlphaCPU *cpu = alpha_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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cs->exception_index = excp;
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env->error_code = error;
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cpu_loop_exit(cs);
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}
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/* This may be called from any of the helpers to set up EXCEPTION_INDEX. */
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void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
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int excp, int error)
|
|
{
|
|
AlphaCPU *cpu = alpha_env_get_cpu(env);
|
|
CPUState *cs = CPU(cpu);
|
|
|
|
cs->exception_index = excp;
|
|
env->error_code = error;
|
|
if (retaddr) {
|
|
cpu_restore_state(cs, retaddr, true);
|
|
/* Floating-point exceptions (our only users) point to the next PC. */
|
|
env->pc += 4;
|
|
}
|
|
cpu_loop_exit(cs);
|
|
}
|
|
|
|
void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr,
|
|
int exc, uint64_t mask)
|
|
{
|
|
env->trap_arg0 = exc;
|
|
env->trap_arg1 = mask;
|
|
dynamic_excp(env, retaddr, EXCP_ARITH, 0);
|
|
}
|