Prepare for, but do not yet implement, the EL2&0 regime. This involves adding the new MMUIdx enumerators and adjusting some of the MMUIdx related predicates to match. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35 lines
719 B
C
35 lines
719 B
C
/*
|
|
* ARM cpu parameters for qemu.
|
|
*
|
|
* Copyright (c) 2003 Fabrice Bellard
|
|
* SPDX-License-Identifier: LGPL-2.0+
|
|
*/
|
|
|
|
#ifndef ARM_CPU_PARAM_H
|
|
#define ARM_CPU_PARAM_H 1
|
|
|
|
#ifdef TARGET_AARCH64
|
|
# define TARGET_LONG_BITS 64
|
|
# define TARGET_PHYS_ADDR_SPACE_BITS 48
|
|
# define TARGET_VIRT_ADDR_SPACE_BITS 48
|
|
#else
|
|
# define TARGET_LONG_BITS 32
|
|
# define TARGET_PHYS_ADDR_SPACE_BITS 40
|
|
# define TARGET_VIRT_ADDR_SPACE_BITS 32
|
|
#endif
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
#define TARGET_PAGE_BITS 12
|
|
#else
|
|
/*
|
|
* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
|
|
* have to support 1K tiny pages.
|
|
*/
|
|
# define TARGET_PAGE_BITS_VARY
|
|
# define TARGET_PAGE_BITS_MIN 10
|
|
#endif
|
|
|
|
#define NB_MMU_MODES 9
|
|
|
|
#endif
|