b9f6033c1a
Prepare for, but do not yet implement, the EL2&0 regime. This involves adding the new MMUIdx enumerators and adjusting some of the MMUIdx related predicates to match. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35 lines
719 B
C
35 lines
719 B
C
/*
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* ARM cpu parameters for qemu.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* SPDX-License-Identifier: LGPL-2.0+
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*/
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#ifndef ARM_CPU_PARAM_H
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#define ARM_CPU_PARAM_H 1
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#ifdef TARGET_AARCH64
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# define TARGET_LONG_BITS 64
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# define TARGET_PHYS_ADDR_SPACE_BITS 48
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# define TARGET_VIRT_ADDR_SPACE_BITS 48
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#else
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# define TARGET_LONG_BITS 32
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# define TARGET_PHYS_ADDR_SPACE_BITS 40
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif
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#ifdef CONFIG_USER_ONLY
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#define TARGET_PAGE_BITS 12
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#else
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/*
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* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
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* have to support 1K tiny pages.
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*/
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# define TARGET_PAGE_BITS_VARY
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# define TARGET_PAGE_BITS_MIN 10
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#endif
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#define NB_MMU_MODES 9
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#endif
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