Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
728 lines
20 KiB
C
728 lines
20 KiB
C
/*
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* QEMU MC146818 RTC emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "pc.h"
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#include "isa.h"
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#include "hpet_emul.h"
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//#define DEBUG_CMOS
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#define RTC_SECONDS 0
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#define RTC_SECONDS_ALARM 1
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#define RTC_MINUTES 2
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#define RTC_MINUTES_ALARM 3
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#define RTC_HOURS 4
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#define RTC_HOURS_ALARM 5
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#define RTC_ALARM_DONT_CARE 0xC0
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#define RTC_DAY_OF_WEEK 6
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#define RTC_DAY_OF_MONTH 7
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#define RTC_MONTH 8
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#define RTC_YEAR 9
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#define RTC_REG_A 10
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#define RTC_REG_B 11
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#define RTC_REG_C 12
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#define RTC_REG_D 13
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#define REG_A_UIP 0x80
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#define REG_B_SET 0x80
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#define REG_B_PIE 0x40
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#define REG_B_AIE 0x20
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#define REG_B_UIE 0x10
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#define REG_B_SQWE 0x08
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#define REG_B_DM 0x04
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#define REG_C_UF 0x10
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#define REG_C_IRQF 0x80
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#define REG_C_PF 0x40
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#define REG_C_AF 0x20
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struct RTCState {
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ISADevice dev;
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uint8_t cmos_data[128];
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uint8_t cmos_index;
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struct tm current_tm;
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int32_t base_year;
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qemu_irq irq;
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qemu_irq sqw_irq;
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int it_shift;
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/* periodic timer */
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QEMUTimer *periodic_timer;
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int64_t next_periodic_time;
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/* second update */
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int64_t next_second_time;
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uint32_t irq_coalesced;
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uint32_t period;
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QEMUTimer *coalesced_timer;
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QEMUTimer *second_timer;
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QEMUTimer *second_timer2;
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};
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static void rtc_irq_raise(qemu_irq irq)
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{
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/* When HPET is operating in legacy mode, RTC interrupts are disabled
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* We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
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* mode is established while interrupt is raised. We want it to
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* be lowered in any case
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*/
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#if defined TARGET_I386
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if (!hpet_in_legacy_mode())
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#endif
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qemu_irq_raise(irq);
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}
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static void rtc_set_time(RTCState *s);
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static void rtc_copy_date(RTCState *s);
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#ifdef TARGET_I386
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static void rtc_coalesced_timer_update(RTCState *s)
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{
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if (s->irq_coalesced == 0) {
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qemu_del_timer(s->coalesced_timer);
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} else {
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/* divide each RTC interval to 2 - 8 smaller intervals */
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int c = MIN(s->irq_coalesced, 7) + 1;
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int64_t next_clock = qemu_get_clock(rtc_clock) +
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muldiv64(s->period / c, get_ticks_per_sec(), 32768);
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qemu_mod_timer(s->coalesced_timer, next_clock);
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}
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}
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static void rtc_coalesced_timer(void *opaque)
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{
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RTCState *s = opaque;
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if (s->irq_coalesced != 0) {
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apic_reset_irq_delivered();
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s->cmos_data[RTC_REG_C] |= 0xc0;
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rtc_irq_raise(s->irq);
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if (apic_get_irq_delivered()) {
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s->irq_coalesced--;
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}
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}
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rtc_coalesced_timer_update(s);
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}
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#endif
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static void rtc_timer_update(RTCState *s, int64_t current_time)
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{
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int period_code, period;
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int64_t cur_clock, next_irq_clock;
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int enable_pie;
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period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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#if defined TARGET_I386
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/* disable periodic timer if hpet is in legacy mode, since interrupts are
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* disabled anyway.
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*/
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enable_pie = !hpet_in_legacy_mode();
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#else
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enable_pie = 1;
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#endif
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if (period_code != 0
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&& (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie)
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|| ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
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if (period_code <= 2)
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period_code += 7;
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/* period in 32 Khz cycles */
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period = 1 << (period_code - 1);
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#ifdef TARGET_I386
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if(period != s->period)
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s->irq_coalesced = (s->irq_coalesced * s->period) / period;
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s->period = period;
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#endif
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/* compute 32 khz clock */
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cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
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next_irq_clock = (cur_clock & ~(period - 1)) + period;
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s->next_periodic_time =
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muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
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qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
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} else {
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#ifdef TARGET_I386
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s->irq_coalesced = 0;
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#endif
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qemu_del_timer(s->periodic_timer);
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}
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}
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static void rtc_periodic_timer(void *opaque)
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{
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RTCState *s = opaque;
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rtc_timer_update(s, s->next_periodic_time);
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if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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s->cmos_data[RTC_REG_C] |= 0xc0;
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#ifdef TARGET_I386
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if(rtc_td_hack) {
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apic_reset_irq_delivered();
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rtc_irq_raise(s->irq);
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if (!apic_get_irq_delivered()) {
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s->irq_coalesced++;
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rtc_coalesced_timer_update(s);
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}
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} else
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#endif
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rtc_irq_raise(s->irq);
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}
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if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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/* Not square wave at all but we don't want 2048Hz interrupts!
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Must be seen as a pulse. */
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qemu_irq_raise(s->sqw_irq);
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}
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}
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static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
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{
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RTCState *s = opaque;
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if ((addr & 1) == 0) {
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s->cmos_index = data & 0x7f;
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} else {
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#ifdef DEBUG_CMOS
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printf("cmos: write index=0x%02x val=0x%02x\n",
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s->cmos_index, data);
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#endif
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switch(s->cmos_index) {
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case RTC_SECONDS_ALARM:
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case RTC_MINUTES_ALARM:
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case RTC_HOURS_ALARM:
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/* XXX: not supported */
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s->cmos_data[s->cmos_index] = data;
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break;
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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s->cmos_data[s->cmos_index] = data;
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/* if in set mode, do not update the time */
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_set_time(s);
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}
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break;
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case RTC_REG_A:
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/* UIP bit is read only */
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s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
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(s->cmos_data[RTC_REG_A] & REG_A_UIP);
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rtc_timer_update(s, qemu_get_clock(rtc_clock));
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break;
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case RTC_REG_B:
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if (data & REG_B_SET) {
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/* set mode: reset UIP mode */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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data &= ~REG_B_UIE;
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} else {
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/* if disabling set mode, update the time */
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if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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rtc_set_time(s);
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}
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}
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s->cmos_data[RTC_REG_B] = data;
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rtc_timer_update(s, qemu_get_clock(rtc_clock));
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break;
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case RTC_REG_C:
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case RTC_REG_D:
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/* cannot write to them */
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break;
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default:
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s->cmos_data[s->cmos_index] = data;
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break;
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}
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}
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}
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static inline int to_bcd(RTCState *s, int a)
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{
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return a;
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} else {
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return ((a / 10) << 4) | (a % 10);
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}
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}
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static inline int from_bcd(RTCState *s, int a)
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{
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return a;
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} else {
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return ((a >> 4) * 10) + (a & 0x0f);
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}
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}
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static void rtc_set_time(RTCState *s)
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{
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struct tm *tm = &s->current_tm;
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tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
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tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
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tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
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(s->cmos_data[RTC_HOURS] & 0x80)) {
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tm->tm_hour += 12;
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}
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tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
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tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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}
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static void rtc_copy_date(RTCState *s)
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{
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const struct tm *tm = &s->current_tm;
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int year;
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s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
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s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
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if (s->cmos_data[RTC_REG_B] & 0x02) {
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/* 24 hour format */
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s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
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} else {
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/* 12 hour format */
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s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
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if (tm->tm_hour >= 12)
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s->cmos_data[RTC_HOURS] |= 0x80;
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}
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s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1);
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s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
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s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
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year = (tm->tm_year - s->base_year) % 100;
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if (year < 0)
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year += 100;
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s->cmos_data[RTC_YEAR] = to_bcd(s, year);
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}
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/* month is between 0 and 11. */
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static int get_days_in_month(int month, int year)
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{
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static const int days_tab[12] = {
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31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
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};
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int d;
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if ((unsigned )month >= 12)
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return 31;
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d = days_tab[month];
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if (month == 1) {
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if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
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d++;
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}
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return d;
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}
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/* update 'tm' to the next second */
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static void rtc_next_second(struct tm *tm)
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{
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int days_in_month;
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tm->tm_sec++;
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if ((unsigned)tm->tm_sec >= 60) {
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tm->tm_sec = 0;
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tm->tm_min++;
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if ((unsigned)tm->tm_min >= 60) {
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tm->tm_min = 0;
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tm->tm_hour++;
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if ((unsigned)tm->tm_hour >= 24) {
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tm->tm_hour = 0;
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/* next day */
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tm->tm_wday++;
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if ((unsigned)tm->tm_wday >= 7)
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tm->tm_wday = 0;
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days_in_month = get_days_in_month(tm->tm_mon,
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tm->tm_year + 1900);
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tm->tm_mday++;
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if (tm->tm_mday < 1) {
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tm->tm_mday = 1;
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} else if (tm->tm_mday > days_in_month) {
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tm->tm_mday = 1;
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tm->tm_mon++;
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if (tm->tm_mon >= 12) {
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tm->tm_mon = 0;
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tm->tm_year++;
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}
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}
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}
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}
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}
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}
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static void rtc_update_second(void *opaque)
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{
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RTCState *s = opaque;
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int64_t delay;
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/* if the oscillator is not in normal operation, we do not update */
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if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
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s->next_second_time += get_ticks_per_sec();
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qemu_mod_timer(s->second_timer, s->next_second_time);
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} else {
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rtc_next_second(&s->current_tm);
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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/* update in progress bit */
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s->cmos_data[RTC_REG_A] |= REG_A_UIP;
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}
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/* should be 244 us = 8 / 32768 seconds, but currently the
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timers do not have the necessary resolution. */
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delay = (get_ticks_per_sec() * 1) / 100;
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if (delay < 1)
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delay = 1;
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qemu_mod_timer(s->second_timer2,
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s->next_second_time + delay);
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}
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}
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static void rtc_update_second2(void *opaque)
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{
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RTCState *s = opaque;
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_copy_date(s);
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}
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/* check alarm */
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if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
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if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
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s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
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((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
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s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
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((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
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s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
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s->cmos_data[RTC_REG_C] |= 0xa0;
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rtc_irq_raise(s->irq);
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}
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}
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/* update ended interrupt */
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s->cmos_data[RTC_REG_C] |= REG_C_UF;
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if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
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s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
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rtc_irq_raise(s->irq);
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}
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/* clear update in progress bit */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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s->next_second_time += get_ticks_per_sec();
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qemu_mod_timer(s->second_timer, s->next_second_time);
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}
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static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
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{
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RTCState *s = opaque;
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int ret;
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if ((addr & 1) == 0) {
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return 0xff;
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} else {
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switch(s->cmos_index) {
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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ret = s->cmos_data[s->cmos_index];
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break;
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case RTC_REG_A:
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ret = s->cmos_data[s->cmos_index];
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break;
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case RTC_REG_C:
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ret = s->cmos_data[s->cmos_index];
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qemu_irq_lower(s->irq);
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s->cmos_data[RTC_REG_C] = 0x00;
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break;
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default:
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ret = s->cmos_data[s->cmos_index];
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break;
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}
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#ifdef DEBUG_CMOS
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printf("cmos: read index=0x%02x val=0x%02x\n",
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s->cmos_index, ret);
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#endif
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return ret;
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}
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}
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|
|
void rtc_set_memory(RTCState *s, int addr, int val)
|
|
{
|
|
if (addr >= 0 && addr <= 127)
|
|
s->cmos_data[addr] = val;
|
|
}
|
|
|
|
void rtc_set_date(RTCState *s, const struct tm *tm)
|
|
{
|
|
s->current_tm = *tm;
|
|
rtc_copy_date(s);
|
|
}
|
|
|
|
/* PC cmos mappings */
|
|
#define REG_IBM_CENTURY_BYTE 0x32
|
|
#define REG_IBM_PS2_CENTURY_BYTE 0x37
|
|
|
|
static void rtc_set_date_from_host(RTCState *s)
|
|
{
|
|
struct tm tm;
|
|
int val;
|
|
|
|
/* set the CMOS date */
|
|
qemu_get_timedate(&tm, 0);
|
|
rtc_set_date(s, &tm);
|
|
|
|
val = to_bcd(s, (tm.tm_year / 100) + 19);
|
|
rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
|
|
rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
|
|
}
|
|
|
|
static int rtc_post_load(void *opaque, int version_id)
|
|
{
|
|
#ifdef TARGET_I386
|
|
RTCState *s = opaque;
|
|
|
|
if (version_id >= 2) {
|
|
if (rtc_td_hack) {
|
|
rtc_coalesced_timer_update(s);
|
|
}
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_rtc = {
|
|
.name = "mc146818rtc",
|
|
.version_id = 2,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.post_load = rtc_post_load,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_BUFFER(cmos_data, RTCState),
|
|
VMSTATE_UINT8(cmos_index, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_sec, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_min, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_hour, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_wday, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_mday, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_mon, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_year, RTCState),
|
|
VMSTATE_TIMER(periodic_timer, RTCState),
|
|
VMSTATE_INT64(next_periodic_time, RTCState),
|
|
VMSTATE_INT64(next_second_time, RTCState),
|
|
VMSTATE_TIMER(second_timer, RTCState),
|
|
VMSTATE_TIMER(second_timer2, RTCState),
|
|
VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
|
VMSTATE_UINT32_V(period, RTCState, 2),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void rtc_reset(void *opaque)
|
|
{
|
|
RTCState *s = opaque;
|
|
|
|
s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
|
|
s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
|
|
|
|
qemu_irq_lower(s->irq);
|
|
|
|
#ifdef TARGET_I386
|
|
if (rtc_td_hack)
|
|
s->irq_coalesced = 0;
|
|
#endif
|
|
}
|
|
|
|
static int rtc_initfn(ISADevice *dev)
|
|
{
|
|
RTCState *s = DO_UPCAST(RTCState, dev, dev);
|
|
int base = 0x70;
|
|
int isairq = 8;
|
|
|
|
isa_init_irq(dev, &s->irq, isairq);
|
|
|
|
s->cmos_data[RTC_REG_A] = 0x26;
|
|
s->cmos_data[RTC_REG_B] = 0x02;
|
|
s->cmos_data[RTC_REG_C] = 0x00;
|
|
s->cmos_data[RTC_REG_D] = 0x80;
|
|
|
|
rtc_set_date_from_host(s);
|
|
|
|
s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
|
|
#ifdef TARGET_I386
|
|
if (rtc_td_hack)
|
|
s->coalesced_timer =
|
|
qemu_new_timer(rtc_clock, rtc_coalesced_timer, s);
|
|
#endif
|
|
s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
|
|
s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
|
|
|
|
s->next_second_time =
|
|
qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
|
|
qemu_mod_timer(s->second_timer2, s->next_second_time);
|
|
|
|
register_ioport_write(base, 2, 1, cmos_ioport_write, s);
|
|
register_ioport_read(base, 2, 1, cmos_ioport_read, s);
|
|
|
|
vmstate_register(base, &vmstate_rtc, s);
|
|
qemu_register_reset(rtc_reset, s);
|
|
return 0;
|
|
}
|
|
|
|
RTCState *rtc_init(int base_year)
|
|
{
|
|
ISADevice *dev;
|
|
|
|
dev = isa_create("mc146818rtc");
|
|
qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
|
qdev_init_nofail(&dev->qdev);
|
|
return DO_UPCAST(RTCState, dev, dev);
|
|
}
|
|
|
|
static ISADeviceInfo mc146818rtc_info = {
|
|
.qdev.name = "mc146818rtc",
|
|
.qdev.size = sizeof(RTCState),
|
|
.qdev.no_user = 1,
|
|
.init = rtc_initfn,
|
|
.qdev.props = (Property[]) {
|
|
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
}
|
|
};
|
|
|
|
static void mc146818rtc_register(void)
|
|
{
|
|
isa_qdev_register(&mc146818rtc_info);
|
|
}
|
|
device_init(mc146818rtc_register)
|
|
|
|
/* Memory mapped interface */
|
|
static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
|
|
{
|
|
RTCState *s = opaque;
|
|
|
|
return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF;
|
|
}
|
|
|
|
static void cmos_mm_writeb (void *opaque,
|
|
target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
RTCState *s = opaque;
|
|
|
|
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
|
}
|
|
|
|
static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
|
|
{
|
|
RTCState *s = opaque;
|
|
uint32_t val;
|
|
|
|
val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap16(val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static void cmos_mm_writew (void *opaque,
|
|
target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
RTCState *s = opaque;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
value = bswap16(value);
|
|
#endif
|
|
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
|
}
|
|
|
|
static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
|
|
{
|
|
RTCState *s = opaque;
|
|
uint32_t val;
|
|
|
|
val = cmos_ioport_read(s, addr >> s->it_shift);
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap32(val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static void cmos_mm_writel (void *opaque,
|
|
target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
RTCState *s = opaque;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
value = bswap32(value);
|
|
#endif
|
|
cmos_ioport_write(s, addr >> s->it_shift, value);
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const rtc_mm_read[] = {
|
|
&cmos_mm_readb,
|
|
&cmos_mm_readw,
|
|
&cmos_mm_readl,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const rtc_mm_write[] = {
|
|
&cmos_mm_writeb,
|
|
&cmos_mm_writew,
|
|
&cmos_mm_writel,
|
|
};
|
|
|
|
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
|
|
int base_year)
|
|
{
|
|
RTCState *s;
|
|
int io_memory;
|
|
|
|
s = qemu_mallocz(sizeof(RTCState));
|
|
|
|
s->irq = irq;
|
|
s->cmos_data[RTC_REG_A] = 0x26;
|
|
s->cmos_data[RTC_REG_B] = 0x02;
|
|
s->cmos_data[RTC_REG_C] = 0x00;
|
|
s->cmos_data[RTC_REG_D] = 0x80;
|
|
|
|
s->base_year = base_year;
|
|
rtc_set_date_from_host(s);
|
|
|
|
s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
|
|
s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
|
|
s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
|
|
|
|
s->next_second_time =
|
|
qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
|
|
qemu_mod_timer(s->second_timer2, s->next_second_time);
|
|
|
|
io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s);
|
|
cpu_register_physical_memory(base, 2 << it_shift, io_memory);
|
|
|
|
vmstate_register(base, &vmstate_rtc, s);
|
|
qemu_register_reset(rtc_reset, s);
|
|
return s;
|
|
}
|