Peter Maydell e1d177b922 target-arm: Set Q bit for overflow in SMUAD and SMLAD ... SMUAD and SMLAD are supposed to set the Q bit if the addition of the two 16x16 multiply products and optional accumulator overflows considered as a signed value. However we were only doing this check for the addition of the accumulator, not when adding the products, with the effect that we were mishandling the edge case where both inputs are 0x80008000. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2011-03-22 07:56:08 +01:00
..
cpu.h	target-arm: Implement cp15 VA->PA translation	2011-03-06 23:37:18 +01:00
exec.h	inline cpu_halted into sole caller	2011-03-13 14:44:21 +00:00
helper.c	target-arm: Fix GE bits for v6media signed modulo arithmetic	2011-03-22 07:52:36 +01:00
helpers.h	target-arm: Move Neon VZIP to helper functions	2011-02-20 17:31:53 +01:00
iwmmxt_helper.c	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00
machine.c	target-arm: Implement cp15 VA->PA translation	2011-03-06 23:37:18 +01:00
neon_helper.c	target-arm: Fix unsigned VQRSHL by large shift counts	2011-02-20 17:43:01 +01:00
op_addsub.h	target-arm: fix addsub/subadd implementation	2010-07-01 23:45:29 +02:00
op_helper.c	Set the right overflow bit for neon 32 and 64 bit saturating add/sub.	2011-02-04 20:57:41 +01:00
translate.c	target-arm: Set Q bit for overflow in SMUAD and SMLAD	2011-03-22 07:56:08 +01:00