Peter Maydell 67e25eed97 TranslatorOps conversion for target/avr ... TranslatorOps conversion for target/cris TranslatorOps conversion for target/nios2 Simple vector operations on TCGv_i32 Host signal fixes for *BSD Improvements to tcg bswap operations -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmDba5cdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+SZwgAmnRoeWUNLSfW+ZAw Zw0QONRmKP/8j4MrW042XDxj+4If2oHkNmgl6IC7xAot0Q+tUJirOwn6pbHkkUbN VplwRvxlXeYcSLPz+yw9omBYZ3RwZfgJ65QamgJ32/+/4W4MqA2Os4zew5kACtE3 oFnpnmLISG5ik1NfxCxtp6aKLgNcRGMHNYnKVlF3HNoOW3gfu4rN5xaCj8diqz0F 73AtVlmqg/IKLE4gK429pZA/0Q+eSUipkDQ0vwKarnehwbXuFduDbSMYcBNOXRm9 TErRIPsNSGxHxIEVJYcY9ZUgrOO39rd5T/r/NONrlwUuDPly2j5FsTTkNFhLJ/h7 HO6xkQ== =UcDr -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210629' into staging TranslatorOps conversion for target/avr TranslatorOps conversion for target/cris TranslatorOps conversion for target/nios2 Simple vector operations on TCGv_i32 Host signal fixes for *BSD Improvements to tcg bswap operations # gpg: Signature made Tue 29 Jun 2021 19:51:03 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210629: (63 commits) tcg/riscv: Remove MO_BSWAP handling tcg/aarch64: Unset TCG_TARGET_HAS_MEMORY_BSWAP tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP target/mips: Fix gen_mxu_s32ldd_s32lddr target/sh4: Improve swap.b translation target/i386: Improve bswap translation target/arm: Improve REVSH target/arm: Improve vector REV target/arm: Improve REV32 tcg: Make use of bswap flags in tcg_gen_qemu_st_* tcg: Make use of bswap flags in tcg_gen_qemu_ld_* tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 tcg: Handle new bswap flags during optimize tcg/tci: Support bswap flags tcg/mips: Support bswap flags in tcg_out_bswap32 tcg/mips: Support bswap flags in tcg_out_bswap16 tcg/s390: Support bswap flags tcg/ppc: Use power10 byte-reverse instructions tcg/ppc: Support bswap flags tcg/ppc: Split out tcg_out_bswap64 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-07-01 20:29:33 +01:00
..
alpha	target/alpha: Honor the FEN bit	2021-06-28 07:27:55 -07:00
arm	target/arm: Improve REVSH	2021-06-29 10:04:57 -07:00
avr	target/avr: Convert to TranslatorOps	2021-06-29 10:04:56 -07:00
cris	target/cris: Do not exit tb for X_FLAG changes	2021-06-29 10:04:56 -07:00
hexagon	Hexagon (target/hexagon) remove unused TCG variables	2021-06-29 11:32:50 -05:00
hppa	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
i386	target/i386: Improve bswap translation	2021-06-29 10:04:57 -07:00
m68k	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
microblaze	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
mips	target/mips: Fix gen_mxu_s32ldd_s32lddr	2021-06-29 10:04:57 -07:00
nios2	target/nios2: Use pc_next for pc + 4	2021-06-29 10:03:11 -07:00
openrisc	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
ppc	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
riscv	target/riscv: gdbstub: Fix dynamic CSR XML generation	2021-06-24 05:00:12 -07:00
rx	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
s390x	tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64	2021-06-29 10:04:57 -07:00
sh4	target/sh4: Improve swap.b translation	2021-06-29 10:04:57 -07:00
sparc	docs: fix references to docs/devel/tracing.rst	2021-06-02 06:51:09 +02:00
tricore	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
xtensa	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
meson.build	Drop the deprecated unicore32 target	2021-05-12 18:20:52 +02:00