SH4 is using 16-bit instructions which means most of the constants are loaded through a constant pool at the end of the subroutine. The same memory page is therefore accessed in exec and read mode. With the current implementation, a QEMU TLB entry is set to read or read/write mode after an UTLB search and to exec mode after an ITLB search, which causes a lot of TLB exceptions to switch from read or read/write to exec and vice versa. This patch optimizes that by already setting the QEMU TLB entry in read or read/write mode when an UTLB entry is copied into ITLB (during an ITLB miss). This improve the emulation speed by about 14%. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
706 lines
18 KiB
C
706 lines
18 KiB
C
/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "hw/sh_intc.h"
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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{
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env->exception_index = -1;
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}
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int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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{
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env->tea = address;
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env->exception_index = -1;
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switch (rw) {
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case 0:
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env->exception_index = 0x0a0;
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break;
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case 1:
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env->exception_index = 0x0c0;
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break;
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case 2:
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env->exception_index = 0x0a0;
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break;
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}
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return 1;
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}
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int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
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{
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/* For user mode, only U0 area is cachable. */
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return !(addr & 0x80000000);
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}
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#else /* !CONFIG_USER_ONLY */
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#define MMU_OK 0
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#define MMU_ITLB_MISS (-1)
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#define MMU_ITLB_MULTIPLE (-2)
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#define MMU_ITLB_VIOLATION (-3)
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#define MMU_DTLB_MISS_READ (-4)
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#define MMU_DTLB_MISS_WRITE (-5)
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#define MMU_DTLB_INITIAL_WRITE (-6)
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#define MMU_DTLB_VIOLATION_READ (-7)
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#define MMU_DTLB_VIOLATION_WRITE (-8)
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#define MMU_DTLB_MULTIPLE (-9)
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#define MMU_DTLB_MISS (-10)
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#define MMU_IADDR_ERROR (-11)
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#define MMU_DADDR_ERROR_READ (-12)
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#define MMU_DADDR_ERROR_WRITE (-13)
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void do_interrupt(CPUState * env)
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{
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int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
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int do_exp, irq_vector = env->exception_index;
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/* prioritize exceptions over interrupts */
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do_exp = env->exception_index != -1;
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do_irq = do_irq && (env->exception_index == -1);
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if (env->sr & SR_BL) {
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if (do_exp && env->exception_index != 0x1e0) {
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env->exception_index = 0x000; /* masked exception -> reset */
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}
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if (do_irq && !env->intr_at_halt) {
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return; /* masked */
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}
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env->intr_at_halt = 0;
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}
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if (do_irq) {
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irq_vector = sh_intc_get_pending_vector(env->intc_handle,
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(env->sr >> 4) & 0xf);
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if (irq_vector == -1) {
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return; /* masked */
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}
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}
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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const char *expname;
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switch (env->exception_index) {
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case 0x0e0:
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expname = "addr_error";
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break;
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case 0x040:
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expname = "tlb_miss";
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break;
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case 0x0a0:
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expname = "tlb_violation";
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break;
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case 0x180:
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expname = "illegal_instruction";
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break;
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case 0x1a0:
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expname = "slot_illegal_instruction";
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break;
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case 0x800:
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expname = "fpu_disable";
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break;
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case 0x820:
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expname = "slot_fpu";
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break;
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case 0x100:
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expname = "data_write";
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break;
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case 0x060:
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expname = "dtlb_miss_write";
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break;
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case 0x0c0:
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expname = "dtlb_violation_write";
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break;
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case 0x120:
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expname = "fpu_exception";
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break;
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case 0x080:
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expname = "initial_page_write";
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break;
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case 0x160:
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expname = "trapa";
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break;
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default:
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expname = do_irq ? "interrupt" : "???";
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break;
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}
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qemu_log("exception 0x%03x [%s] raised\n",
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irq_vector, expname);
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log_cpu_state(env, 0);
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}
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env->ssr = env->sr;
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env->spc = env->pc;
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env->sgr = env->gregs[15];
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env->sr |= SR_BL | SR_MD | SR_RB;
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if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
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/* Branch instruction should be executed again before delay slot. */
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env->spc -= 2;
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/* Clear flags for exception/interrupt routine. */
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env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
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}
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if (env->flags & DELAY_SLOT_CLEARME)
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env->flags = 0;
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if (do_exp) {
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env->expevt = env->exception_index;
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switch (env->exception_index) {
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case 0x000:
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case 0x020:
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case 0x140:
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env->sr &= ~SR_FD;
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env->sr |= 0xf << 4; /* IMASK */
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env->pc = 0xa0000000;
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break;
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case 0x040:
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case 0x060:
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env->pc = env->vbr + 0x400;
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break;
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case 0x160:
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env->spc += 2; /* special case for TRAPA */
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/* fall through */
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default:
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env->pc = env->vbr + 0x100;
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break;
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}
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return;
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}
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if (do_irq) {
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env->intevt = irq_vector;
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env->pc = env->vbr + 0x600;
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return;
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}
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}
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static void update_itlb_use(CPUState * env, int itlbnb)
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{
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uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
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switch (itlbnb) {
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case 0:
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and_mask = 0x1f;
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break;
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case 1:
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and_mask = 0xe7;
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or_mask = 0x80;
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break;
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case 2:
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and_mask = 0xfb;
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or_mask = 0x50;
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break;
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case 3:
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or_mask = 0x2c;
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break;
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}
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env->mmucr &= (and_mask << 24) | 0x00ffffff;
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env->mmucr |= (or_mask << 24);
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}
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static int itlb_replacement(CPUState * env)
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{
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if ((env->mmucr & 0xe0000000) == 0xe0000000)
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return 0;
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if ((env->mmucr & 0x98000000) == 0x18000000)
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return 1;
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if ((env->mmucr & 0x54000000) == 0x04000000)
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return 2;
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if ((env->mmucr & 0x2c000000) == 0x00000000)
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return 3;
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cpu_abort(env, "Unhandled itlb_replacement");
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}
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/* Find the corresponding entry in the right TLB
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Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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*/
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static int find_tlb_entry(CPUState * env, target_ulong address,
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tlb_t * entries, uint8_t nbtlb, int use_asid)
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{
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int match = MMU_DTLB_MISS;
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uint32_t start, end;
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uint8_t asid;
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int i;
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asid = env->pteh & 0xff;
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for (i = 0; i < nbtlb; i++) {
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if (!entries[i].v)
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continue; /* Invalid entry */
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if (!entries[i].sh && use_asid && entries[i].asid != asid)
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continue; /* Bad ASID */
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start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
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end = start + entries[i].size - 1;
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if (address >= start && address <= end) { /* Match */
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if (match != MMU_DTLB_MISS)
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return MMU_DTLB_MULTIPLE; /* Multiple match */
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match = i;
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}
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}
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return match;
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}
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static void increment_urc(CPUState * env)
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{
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uint8_t urb, urc;
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/* Increment URC */
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urb = ((env->mmucr) >> 18) & 0x3f;
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urc = ((env->mmucr) >> 10) & 0x3f;
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urc++;
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if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
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urc = 0;
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env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
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}
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/* Copy and utlb entry into itlb
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Return entry
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*/
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static int copy_utlb_entry_itlb(CPUState *env, int utlb)
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{
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int itlb;
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tlb_t * ientry;
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itlb = itlb_replacement(env);
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ientry = &env->itlb[itlb];
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if (ientry->v) {
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tlb_flush_page(env, ientry->vpn << 10);
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}
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*ientry = env->utlb[utlb];
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update_itlb_use(env, itlb);
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return itlb;
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}
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/* Find itlb entry
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Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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*/
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static int find_itlb_entry(CPUState * env, target_ulong address,
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int use_asid)
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{
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int e;
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e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
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if (e == MMU_DTLB_MULTIPLE) {
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e = MMU_ITLB_MULTIPLE;
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} else if (e == MMU_DTLB_MISS) {
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e = MMU_ITLB_MISS;
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} else if (e >= 0) {
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update_itlb_use(env, e);
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}
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return e;
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}
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/* Find utlb entry
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Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
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static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
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{
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/* per utlb access */
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increment_urc(env);
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/* Return entry */
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return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
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}
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/* Match address against MMU
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Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
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MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
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MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
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MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
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MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
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*/
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static int get_mmu_address(CPUState * env, target_ulong * physical,
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int *prot, target_ulong address,
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int rw, int access_type)
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{
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int use_asid, n;
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tlb_t *matching = NULL;
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use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
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if (rw == 2) {
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n = find_itlb_entry(env, address, use_asid);
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if (n >= 0) {
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matching = &env->itlb[n];
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if (!(env->sr & SR_MD) && !(matching->pr & 2))
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n = MMU_ITLB_VIOLATION;
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else
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*prot = PAGE_EXEC;
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} else {
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n = find_utlb_entry(env, address, use_asid);
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if (n >= 0) {
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n = copy_utlb_entry_itlb(env, n);
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matching = &env->itlb[n];
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if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
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n = MMU_ITLB_VIOLATION;
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} else {
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*prot = PAGE_READ | PAGE_EXEC;
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if ((matching->pr & 1) && matching->d) {
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*prot |= PAGE_WRITE;
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}
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}
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} else if (n == MMU_DTLB_MULTIPLE) {
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n = MMU_ITLB_MULTIPLE;
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} else if (n == MMU_DTLB_MISS) {
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n = MMU_ITLB_MISS;
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}
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}
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} else {
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n = find_utlb_entry(env, address, use_asid);
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if (n >= 0) {
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matching = &env->utlb[n];
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if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
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n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
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MMU_DTLB_VIOLATION_READ;
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} else if ((rw == 1) && !(matching->pr & 1)) {
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n = MMU_DTLB_VIOLATION_WRITE;
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} else if ((rw == 1) & !matching->d) {
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n = MMU_DTLB_INITIAL_WRITE;
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} else {
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*prot = PAGE_READ;
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if ((matching->pr & 1) && matching->d) {
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*prot |= PAGE_WRITE;
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}
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}
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} else if (n == MMU_DTLB_MISS) {
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n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
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MMU_DTLB_MISS_READ;
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}
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}
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if (n >= 0) {
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n = MMU_OK;
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*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
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(address & (matching->size - 1));
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}
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return n;
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}
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static int get_physical_address(CPUState * env, target_ulong * physical,
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int *prot, target_ulong address,
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int rw, int access_type)
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{
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/* P1, P2 and P4 areas do not use translation */
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if ((address >= 0x80000000 && address < 0xc0000000) ||
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address >= 0xe0000000) {
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if (!(env->sr & SR_MD)
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&& (address < 0xe0000000 || address >= 0xe4000000)) {
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/* Unauthorized access in user mode (only store queues are available) */
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fprintf(stderr, "Unauthorized access\n");
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if (rw == 0)
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return MMU_DADDR_ERROR_READ;
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else if (rw == 1)
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return MMU_DADDR_ERROR_WRITE;
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else
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return MMU_IADDR_ERROR;
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}
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if (address >= 0x80000000 && address < 0xc0000000) {
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/* Mask upper 3 bits for P1 and P2 areas */
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*physical = address & 0x1fffffff;
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} else {
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*physical = address;
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}
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return MMU_OK;
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}
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/* If MMU is disabled, return the corresponding physical page */
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if (!env->mmucr & MMUCR_AT) {
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*physical = address & 0x1FFFFFFF;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return MMU_OK;
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}
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/* We need to resort to the MMU */
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return get_mmu_address(env, physical, prot, address, rw, access_type);
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}
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int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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{
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target_ulong physical;
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int prot, ret, access_type;
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access_type = ACCESS_INT;
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ret =
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get_physical_address(env, &physical, &prot, address, rw,
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access_type);
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if (ret != MMU_OK) {
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env->tea = address;
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switch (ret) {
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case MMU_ITLB_MISS:
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case MMU_DTLB_MISS_READ:
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env->exception_index = 0x040;
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break;
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case MMU_DTLB_MULTIPLE:
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case MMU_ITLB_MULTIPLE:
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env->exception_index = 0x140;
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break;
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case MMU_ITLB_VIOLATION:
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env->exception_index = 0x0a0;
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break;
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case MMU_DTLB_MISS_WRITE:
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env->exception_index = 0x060;
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break;
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case MMU_DTLB_INITIAL_WRITE:
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env->exception_index = 0x080;
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break;
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case MMU_DTLB_VIOLATION_READ:
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env->exception_index = 0x0a0;
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break;
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case MMU_DTLB_VIOLATION_WRITE:
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env->exception_index = 0x0c0;
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break;
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case MMU_IADDR_ERROR:
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case MMU_DADDR_ERROR_READ:
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env->exception_index = 0x0c0;
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break;
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case MMU_DADDR_ERROR_WRITE:
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env->exception_index = 0x100;
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break;
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default:
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cpu_abort(env, "Unhandled MMU fault");
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}
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return 1;
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}
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address &= TARGET_PAGE_MASK;
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physical &= TARGET_PAGE_MASK;
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tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
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return 0;
|
|
}
|
|
|
|
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
|
|
{
|
|
target_ulong physical;
|
|
int prot;
|
|
|
|
get_physical_address(env, &physical, &prot, addr, 0, 0);
|
|
return physical;
|
|
}
|
|
|
|
void cpu_load_tlb(CPUSH4State * env)
|
|
{
|
|
int n = cpu_mmucr_urc(env->mmucr);
|
|
tlb_t * entry = &env->utlb[n];
|
|
|
|
if (entry->v) {
|
|
/* Overwriting valid entry in utlb. */
|
|
target_ulong address = entry->vpn << 10;
|
|
tlb_flush_page(env, address);
|
|
}
|
|
|
|
/* Take values into cpu status from registers. */
|
|
entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
|
|
entry->vpn = cpu_pteh_vpn(env->pteh);
|
|
entry->v = (uint8_t)cpu_ptel_v(env->ptel);
|
|
entry->ppn = cpu_ptel_ppn(env->ptel);
|
|
entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
|
|
switch (entry->sz) {
|
|
case 0: /* 00 */
|
|
entry->size = 1024; /* 1K */
|
|
break;
|
|
case 1: /* 01 */
|
|
entry->size = 1024 * 4; /* 4K */
|
|
break;
|
|
case 2: /* 10 */
|
|
entry->size = 1024 * 64; /* 64K */
|
|
break;
|
|
case 3: /* 11 */
|
|
entry->size = 1024 * 1024; /* 1M */
|
|
break;
|
|
default:
|
|
cpu_abort(env, "Unhandled load_tlb");
|
|
break;
|
|
}
|
|
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
|
|
entry->c = (uint8_t)cpu_ptel_c(env->ptel);
|
|
entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
|
|
entry->d = (uint8_t)cpu_ptel_d(env->ptel);
|
|
entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
|
|
entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
|
|
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
|
|
}
|
|
|
|
void cpu_sh4_invalidate_tlb(CPUSH4State *s)
|
|
{
|
|
int i;
|
|
|
|
/* UTLB */
|
|
for (i = 0; i < UTLB_SIZE; i++) {
|
|
tlb_t * entry = &s->utlb[i];
|
|
entry->v = 0;
|
|
}
|
|
/* ITLB */
|
|
for (i = 0; i < UTLB_SIZE; i++) {
|
|
tlb_t * entry = &s->utlb[i];
|
|
entry->v = 0;
|
|
}
|
|
|
|
tlb_flush(s, 1);
|
|
}
|
|
|
|
void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
|
|
uint32_t mem_value)
|
|
{
|
|
uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
|
|
uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
|
|
uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
|
|
|
int index = (addr & 0x00003f00) >> 8;
|
|
tlb_t * entry = &s->itlb[index];
|
|
if (entry->v) {
|
|
/* Overwriting valid entry in itlb. */
|
|
target_ulong address = entry->vpn << 10;
|
|
tlb_flush_page(s, address);
|
|
}
|
|
entry->asid = asid;
|
|
entry->vpn = vpn;
|
|
entry->v = v;
|
|
}
|
|
|
|
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
|
|
uint32_t mem_value)
|
|
{
|
|
int associate = addr & 0x0000080;
|
|
uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
|
|
uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
|
|
uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
|
|
uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
|
int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
|
|
|
|
if (associate) {
|
|
int i;
|
|
tlb_t * utlb_match_entry = NULL;
|
|
int needs_tlb_flush = 0;
|
|
|
|
/* search UTLB */
|
|
for (i = 0; i < UTLB_SIZE; i++) {
|
|
tlb_t * entry = &s->utlb[i];
|
|
if (!entry->v)
|
|
continue;
|
|
|
|
if (entry->vpn == vpn
|
|
&& (!use_asid || entry->asid == asid || entry->sh)) {
|
|
if (utlb_match_entry) {
|
|
/* Multiple TLB Exception */
|
|
s->exception_index = 0x140;
|
|
s->tea = addr;
|
|
break;
|
|
}
|
|
if (entry->v && !v)
|
|
needs_tlb_flush = 1;
|
|
entry->v = v;
|
|
entry->d = d;
|
|
utlb_match_entry = entry;
|
|
}
|
|
increment_urc(s); /* per utlb access */
|
|
}
|
|
|
|
/* search ITLB */
|
|
for (i = 0; i < ITLB_SIZE; i++) {
|
|
tlb_t * entry = &s->itlb[i];
|
|
if (entry->vpn == vpn
|
|
&& (!use_asid || entry->asid == asid || entry->sh)) {
|
|
if (entry->v && !v)
|
|
needs_tlb_flush = 1;
|
|
if (utlb_match_entry)
|
|
*entry = *utlb_match_entry;
|
|
else
|
|
entry->v = v;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (needs_tlb_flush)
|
|
tlb_flush_page(s, vpn << 10);
|
|
|
|
} else {
|
|
int index = (addr & 0x00003f00) >> 8;
|
|
tlb_t * entry = &s->utlb[index];
|
|
if (entry->v) {
|
|
/* Overwriting valid entry in utlb. */
|
|
target_ulong address = entry->vpn << 10;
|
|
tlb_flush_page(s, address);
|
|
}
|
|
entry->asid = asid;
|
|
entry->vpn = vpn;
|
|
entry->d = d;
|
|
entry->v = v;
|
|
increment_urc(s);
|
|
}
|
|
}
|
|
|
|
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
|
|
{
|
|
int n;
|
|
int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
|
|
|
|
/* check area */
|
|
if (env->sr & SR_MD) {
|
|
/* For previledged mode, P2 and P4 area is not cachable. */
|
|
if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
|
|
return 0;
|
|
} else {
|
|
/* For user mode, only U0 area is cachable. */
|
|
if (0x80000000 <= addr)
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* TODO : Evaluate CCR and check if the cache is on or off.
|
|
* Now CCR is not in CPUSH4State, but in SH7750State.
|
|
* When you move the ccr inot CPUSH4State, the code will be
|
|
* as follows.
|
|
*/
|
|
#if 0
|
|
/* check if operand cache is enabled or not. */
|
|
if (!(env->ccr & 1))
|
|
return 0;
|
|
#endif
|
|
|
|
/* if MMU is off, no check for TLB. */
|
|
if (env->mmucr & MMUCR_AT)
|
|
return 1;
|
|
|
|
/* check TLB */
|
|
n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
|
|
if (n >= 0)
|
|
return env->itlb[n].c;
|
|
|
|
n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
|
|
if (n >= 0)
|
|
return env->utlb[n].c;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif
|