Fix potential overflow problem when calculating pwm_duty. 1. Ensure p->cmr and p->cnr to be from [0,65535], according to the hardware specification. 2. Changed duty to uint32_t. However, since MAX_DUTY * (p->cmr+1) can excceed UINT32_MAX, we convert them to uint64_t in computation and converted them back to uint32_t. (duty is guaranteed to be <= MAX_DUTY so it won't overflow.) Fixes: CID 1442342 Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Doug Evans <dje@google.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210127011142.2122790-1-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
494 lines
13 KiB
C
494 lines
13 KiB
C
/*
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* QTests for Nuvoton NPCM7xx PWM Modules.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "libqos/libqtest.h"
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#include "qapi/qmp/qdict.h"
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#include "qapi/qmp/qnum.h"
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#define REF_HZ 25000000
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/* Register field definitions. */
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#define CH_EN BIT(0)
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#define CH_INV BIT(2)
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#define CH_MOD BIT(3)
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/* Registers shared between all PWMs in a module */
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#define PPR 0x00
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#define CSR 0x04
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#define PCR 0x08
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#define PIER 0x3c
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#define PIIR 0x40
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/* CLK module related */
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#define CLK_BA 0xf0801000
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#define CLKSEL 0x04
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#define CLKDIV1 0x08
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#define CLKDIV2 0x2c
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#define PLLCON0 0x0c
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#define PLLCON1 0x10
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#define PLL_INDV(rv) extract32((rv), 0, 6)
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#define PLL_FBDV(rv) extract32((rv), 16, 12)
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#define PLL_OTDV1(rv) extract32((rv), 8, 3)
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#define PLL_OTDV2(rv) extract32((rv), 13, 3)
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#define APB3CKDIV(rv) extract32((rv), 28, 2)
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#define CLK2CKDIV(rv) extract32((rv), 0, 1)
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#define CLK4CKDIV(rv) extract32((rv), 26, 2)
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#define CPUCKSEL(rv) extract32((rv), 0, 2)
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#define MAX_DUTY 1000000
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typedef struct PWMModule {
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int irq;
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uint64_t base_addr;
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} PWMModule;
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typedef struct PWM {
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uint32_t cnr_offset;
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uint32_t cmr_offset;
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uint32_t pdr_offset;
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uint32_t pwdr_offset;
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} PWM;
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typedef struct TestData {
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const PWMModule *module;
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const PWM *pwm;
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} TestData;
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static const PWMModule pwm_module_list[] = {
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{
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.irq = 93,
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.base_addr = 0xf0103000
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},
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{
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.irq = 94,
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.base_addr = 0xf0104000
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}
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};
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static const PWM pwm_list[] = {
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{
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.cnr_offset = 0x0c,
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.cmr_offset = 0x10,
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.pdr_offset = 0x14,
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.pwdr_offset = 0x44,
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},
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{
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.cnr_offset = 0x18,
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.cmr_offset = 0x1c,
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.pdr_offset = 0x20,
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.pwdr_offset = 0x48,
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},
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{
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.cnr_offset = 0x24,
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.cmr_offset = 0x28,
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.pdr_offset = 0x2c,
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.pwdr_offset = 0x4c,
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},
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{
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.cnr_offset = 0x30,
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.cmr_offset = 0x34,
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.pdr_offset = 0x38,
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.pwdr_offset = 0x50,
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},
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};
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static const int ppr_base[] = { 0, 0, 8, 8 };
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static const int csr_base[] = { 0, 4, 8, 12 };
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static const int pcr_base[] = { 0, 8, 12, 16 };
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static const uint32_t ppr_list[] = {
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0,
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1,
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10,
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100,
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255, /* Max possible value. */
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};
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static const uint32_t csr_list[] = {
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0,
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1,
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2,
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3,
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4, /* Max possible value. */
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};
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static const uint32_t cnr_list[] = {
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0,
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1,
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50,
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100,
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150,
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200,
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1000,
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10000,
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65535, /* Max possible value. */
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};
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static const uint32_t cmr_list[] = {
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0,
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1,
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10,
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50,
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100,
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150,
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200,
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1000,
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10000,
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65535, /* Max possible value. */
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};
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/* Returns the index of the PWM module. */
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static int pwm_module_index(const PWMModule *module)
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{
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ptrdiff_t diff = module - pwm_module_list;
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g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
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return diff;
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}
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/* Returns the index of the PWM entry. */
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static int pwm_index(const PWM *pwm)
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{
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ptrdiff_t diff = pwm - pwm_list;
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g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
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return diff;
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}
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static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
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{
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QDict *response;
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uint64_t val;
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g_test_message("Getting properties %s from %s", name, path);
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response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
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" 'arguments': { 'path': %s, 'property': %s}}",
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path, name);
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/* The qom set message returns successfully. */
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g_assert_true(qdict_haskey(response, "return"));
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val = qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
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qobject_unref(response);
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return val;
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}
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static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
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{
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char path[100];
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char name[100];
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sprintf(path, "/machine/soc/pwm[%d]", module_index);
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sprintf(name, "freq[%d]", pwm_index);
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return pwm_qom_get(qts, path, name);
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}
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static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
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{
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char path[100];
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char name[100];
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sprintf(path, "/machine/soc/pwm[%d]", module_index);
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sprintf(name, "duty[%d]", pwm_index);
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return pwm_qom_get(qts, path, name);
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}
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static uint32_t get_pll(uint32_t con)
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{
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return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
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* PLL_OTDV2(con));
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}
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static uint64_t read_pclk(QTestState *qts)
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{
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uint64_t freq = REF_HZ;
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uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
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uint32_t pllcon;
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uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
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uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
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switch (CPUCKSEL(clksel)) {
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case 0:
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pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
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freq = get_pll(pllcon);
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break;
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case 1:
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pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
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freq = get_pll(pllcon);
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break;
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case 2:
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break;
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case 3:
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break;
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default:
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g_assert_not_reached();
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}
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freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
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return freq;
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}
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static uint32_t pwm_selector(uint32_t csr)
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{
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switch (csr) {
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case 0:
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return 2;
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case 1:
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return 4;
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case 2:
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return 8;
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case 3:
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return 16;
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case 4:
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return 1;
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default:
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g_assert_not_reached();
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}
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}
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static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
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uint32_t cnr)
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{
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return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
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}
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static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
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{
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uint32_t duty;
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if (cnr == 0) {
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/* PWM is stopped. */
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duty = 0;
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} else if (cmr >= cnr) {
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duty = MAX_DUTY;
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} else {
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duty = (uint64_t)MAX_DUTY * (cmr + 1) / (cnr + 1);
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}
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if (inverted) {
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duty = MAX_DUTY - duty;
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}
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return duty;
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}
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static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
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{
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return qtest_readl(qts, td->module->base_addr + offset);
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}
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static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
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uint32_t value)
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{
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qtest_writel(qts, td->module->base_addr + offset, value);
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}
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static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
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{
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return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
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}
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static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
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{
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pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
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}
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static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
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{
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return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
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}
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static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
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{
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pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
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}
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static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
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{
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return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
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}
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static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
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{
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pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
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}
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static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
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{
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return pwm_read(qts, td, td->pwm->cnr_offset);
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}
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static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
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{
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pwm_write(qts, td, td->pwm->cnr_offset, value);
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}
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static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
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{
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return pwm_read(qts, td, td->pwm->cmr_offset);
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}
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static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
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{
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pwm_write(qts, td, td->pwm->cmr_offset, value);
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}
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/* Check pwm registers can be reset to default value */
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static void test_init(gconstpointer test_data)
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{
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const TestData *td = test_data;
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QTestState *qts = qtest_init("-machine quanta-gsj");
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int module = pwm_module_index(td->module);
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int pwm = pwm_index(td->pwm);
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g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
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g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
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qtest_quit(qts);
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}
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/* One-shot mode should not change frequency and duty cycle. */
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static void test_oneshot(gconstpointer test_data)
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{
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const TestData *td = test_data;
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QTestState *qts = qtest_init("-machine quanta-gsj");
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int module = pwm_module_index(td->module);
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int pwm = pwm_index(td->pwm);
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uint32_t ppr, csr, pcr;
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int i, j;
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pcr = CH_EN;
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for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
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ppr = ppr_list[i];
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pwm_write_ppr(qts, td, ppr);
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for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
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csr = csr_list[j];
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pwm_write_csr(qts, td, csr);
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pwm_write_pcr(qts, td, pcr);
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g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
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g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
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g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
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g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
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g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
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}
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}
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qtest_quit(qts);
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}
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/* In toggle mode, the PWM generates correct outputs. */
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static void test_toggle(gconstpointer test_data)
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{
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const TestData *td = test_data;
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QTestState *qts = qtest_init("-machine quanta-gsj");
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int module = pwm_module_index(td->module);
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int pwm = pwm_index(td->pwm);
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uint32_t ppr, csr, pcr, cnr, cmr;
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int i, j, k, l;
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uint64_t expected_freq, expected_duty;
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pcr = CH_EN | CH_MOD;
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for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
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ppr = ppr_list[i];
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pwm_write_ppr(qts, td, ppr);
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for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
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csr = csr_list[j];
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pwm_write_csr(qts, td, csr);
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for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
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cnr = cnr_list[k];
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pwm_write_cnr(qts, td, cnr);
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for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
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cmr = cmr_list[l];
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pwm_write_cmr(qts, td, cmr);
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expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
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expected_duty = pwm_compute_duty(cnr, cmr, false);
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pwm_write_pcr(qts, td, pcr);
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g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
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g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
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g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
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g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
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g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
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g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
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==, expected_duty);
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if (expected_duty != 0 && expected_duty != 100) {
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/* Duty cycle with 0 or 100 doesn't need frequency. */
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g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
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==, expected_freq);
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}
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/* Test inverted mode */
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expected_duty = pwm_compute_duty(cnr, cmr, true);
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pwm_write_pcr(qts, td, pcr | CH_INV);
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g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
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g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
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==, expected_duty);
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if (expected_duty != 0 && expected_duty != 100) {
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/* Duty cycle with 0 or 100 doesn't need frequency. */
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g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
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==, expected_freq);
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}
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}
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}
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}
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}
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qtest_quit(qts);
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}
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static void pwm_add_test(const char *name, const TestData* td,
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GTestDataFunc fn)
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{
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g_autofree char *full_name = g_strdup_printf(
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"npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
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pwm_index(td->pwm), name);
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qtest_add_data_func(full_name, td, fn);
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}
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#define add_test(name, td) pwm_add_test(#name, td, test_##name)
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int main(int argc, char **argv)
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{
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TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
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g_test_init(&argc, &argv, NULL);
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|
for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
|
|
for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
|
|
TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
|
|
|
|
td->module = &pwm_module_list[i];
|
|
td->pwm = &pwm_list[j];
|
|
|
|
add_test(init, td);
|
|
add_test(oneshot, td);
|
|
add_test(toggle, td);
|
|
}
|
|
}
|
|
|
|
return g_test_run();
|
|
}
|