The pseries machine type implements the behaviour of a PAPR compliant hypervisor, without actually executing such a hypervisor on the virtual CPU. To do this we need some hooks in the CPU code to make hypervisor facilities get redirected to the machine instead of emulated internally. For hypercalls this is managed through the cpu->vhyp field, which points to a QOM interface with a method implementing the hypercall. For the hashed page table (HPT) - also a hypervisor resource - we use an older hack. CPUPPCState has an 'external_htab' field which when non-NULL indicates that the HPT is stored in qemu memory, rather than within the guest's address space. For consistency - and to make some future extensions easier - this merges the external HPT mechanism into the vhyp mechanism. Methods are added to vhyp for the basic operations the core hash MMU code needs: map_hptes() and unmap_hptes() for reading the HPT, store_hpte() for updating it and hpt_mask() to retrieve its size. To match this, the pseries machine now sets these vhyp fields in its existing vhyp class, rather than reaching into the cpu object to set the external_htab field. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
284 lines
7.4 KiB
C
284 lines
7.4 KiB
C
/*
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* sPAPR CPU core device, acts as container of CPU thread devices.
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*
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* Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "hw/cpu/core.h"
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#include "hw/ppc/spapr_cpu_core.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/spapr.h"
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#include "hw/boards.h"
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#include "qapi/error.h"
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#include "sysemu/cpus.h"
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#include "sysemu/kvm.h"
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#include "target/ppc/kvm_ppc.h"
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#include "hw/ppc/ppc.h"
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#include "target/ppc/mmu-hash64.h"
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#include "sysemu/numa.h"
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#include "qemu/error-report.h"
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static void spapr_cpu_reset(void *opaque)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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PowerPCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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cpu_reset(cs);
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/* All CPUs start halted. CPU0 is unhalted from the machine level
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* reset code and the rest are explicitly started up by the guest
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* using an RTAS call */
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cs->halted = 1;
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env->spr[SPR_HIOR] = 0;
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/*
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* This is a hack for the benefit of KVM PR - it abuses the SDR1
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* slot in kvm_sregs to communicate the userspace address of the
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* HPT
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*/
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if (kvm_enabled()) {
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env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab
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| (spapr->htab_shift - 18);
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if (kvmppc_put_books_sregs(cpu) < 0) {
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error_report("Unable to update SDR1 in KVM");
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exit(1);
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}
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}
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}
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static void spapr_cpu_destroy(PowerPCCPU *cpu)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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xics_cpu_destroy(spapr->xics, cpu);
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qemu_unregister_reset(spapr_cpu_reset, cpu);
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}
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static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
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Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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int i;
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
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/* Enable PAPR mode in TCG or KVM */
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cpu_ppc_set_papr(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
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if (cpu->max_compat) {
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Error *local_err = NULL;
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ppc_set_compat(cpu, cpu->max_compat, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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/* Set NUMA node for the added CPUs */
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i = numa_get_node_for_cpu(cs->cpu_index);
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if (i < nb_numa_nodes) {
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cs->numa_node = i;
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}
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xics_cpu_setup(spapr->xics, cpu);
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qemu_register_reset(spapr_cpu_reset, cpu);
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spapr_cpu_reset(cpu);
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}
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/*
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* Return the sPAPR CPU core type for @model which essentially is the CPU
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* model specified with -cpu cmdline option.
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*/
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char *spapr_get_cpu_core_type(const char *model)
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{
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char *core_type;
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gchar **model_pieces = g_strsplit(model, ",", 2);
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core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE);
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/* Check whether it exists or whether we have to look up an alias name */
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if (!object_class_by_name(core_type)) {
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const char *realmodel;
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g_free(core_type);
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core_type = NULL;
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realmodel = ppc_cpu_lookup_alias(model_pieces[0]);
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if (realmodel) {
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core_type = spapr_get_cpu_core_type(realmodel);
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}
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}
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g_strfreev(model_pieces);
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return core_type;
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}
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static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp)
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{
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sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
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const char *typename = object_class_get_name(scc->cpu_class);
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size_t size = object_type_get_instance_size(typename);
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CPUCore *cc = CPU_CORE(dev);
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int i;
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for (i = 0; i < cc->nr_threads; i++) {
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void *obj = sc->threads + i * size;
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DeviceState *dev = DEVICE(obj);
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CPUState *cs = CPU(dev);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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spapr_cpu_destroy(cpu);
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cpu_remove_sync(cs);
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object_unparent(obj);
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}
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g_free(sc->threads);
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}
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static void spapr_cpu_core_realize_child(Object *child, Error **errp)
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{
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Error *local_err = NULL;
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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CPUState *cs = CPU(child);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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object_property_set_bool(child, true, "realized", &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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spapr_cpu_init(spapr, cpu, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
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{
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sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
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CPUCore *cc = CPU_CORE(OBJECT(dev));
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const char *typename = object_class_get_name(scc->cpu_class);
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size_t size = object_type_get_instance_size(typename);
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Error *local_err = NULL;
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void *obj;
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int i, j;
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sc->threads = g_malloc0(size * cc->nr_threads);
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for (i = 0; i < cc->nr_threads; i++) {
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char id[32];
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CPUState *cs;
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obj = sc->threads + i * size;
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object_initialize(obj, size, typename);
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cs = CPU(obj);
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cs->cpu_index = cc->core_id + i;
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snprintf(id, sizeof(id), "thread[%d]", i);
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object_property_add_child(OBJECT(sc), id, obj, &local_err);
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if (local_err) {
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goto err;
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}
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object_unref(obj);
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}
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for (j = 0; j < cc->nr_threads; j++) {
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obj = sc->threads + j * size;
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spapr_cpu_core_realize_child(obj, &local_err);
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if (local_err) {
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goto err;
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}
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}
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return;
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err:
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while (--i >= 0) {
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obj = sc->threads + i * size;
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object_unparent(obj);
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}
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g_free(sc->threads);
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error_propagate(errp, local_err);
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}
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static const char *spapr_core_models[] = {
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/* 970 */
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"970_v2.2",
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/* 970MP variants */
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"970MP_v1.0",
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"970mp_v1.0",
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"970MP_v1.1",
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"970mp_v1.1",
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/* POWER5+ */
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"POWER5+_v2.1",
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/* POWER7 */
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"POWER7_v2.3",
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/* POWER7+ */
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"POWER7+_v2.1",
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/* POWER8 */
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"POWER8_v2.0",
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/* POWER8E */
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"POWER8E_v2.1",
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/* POWER8NVL */
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"POWER8NVL_v1.0",
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};
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void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
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dc->realize = spapr_cpu_core_realize;
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dc->unrealize = spapr_cpu_core_unrealizefn;
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scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data);
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g_assert(scc->cpu_class);
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}
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static const TypeInfo spapr_cpu_core_type_info = {
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.name = TYPE_SPAPR_CPU_CORE,
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.parent = TYPE_CPU_CORE,
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.abstract = true,
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.instance_size = sizeof(sPAPRCPUCore),
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.class_size = sizeof(sPAPRCPUCoreClass),
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};
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static void spapr_cpu_core_register_types(void)
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{
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int i;
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type_register_static(&spapr_cpu_core_type_info);
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for (i = 0; i < ARRAY_SIZE(spapr_core_models); i++) {
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TypeInfo type_info = {
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.parent = TYPE_SPAPR_CPU_CORE,
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.instance_size = sizeof(sPAPRCPUCore),
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.class_init = spapr_cpu_core_class_init,
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.class_data = (void *) spapr_core_models[i],
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};
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type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE,
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spapr_core_models[i]);
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type_register(&type_info);
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g_free((void *)type_info.name);
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}
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}
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type_init(spapr_cpu_core_register_types)
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