e6ae5981ea
We currently store the M profile CPU register state PRIMASK and FAULTMASK in the daif field of the CPU state in its I and F bits. This is a legacy from the original implementation, which tried to share the cpu_exec_interrupt code between A profile and M profile. We've since separated out the two cases because they are significantly different, so now there is no common code between M and A profile which looks at env->daif: all the uses are either in A-only or M-only code paths. Sharing the state fields now is just confusing, and will make things awkward when we implement v8M, where the PRIMASK and FAULTMASK registers are banked between security states. Switch M profile over to using v7m.faultmask and v7m.primask fields for these registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1501692241-23310-10-git-send-email-peter.maydell@linaro.org
445 lines
13 KiB
C
445 lines
13 KiB
C
#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "qemu/error-report.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#include "internals.h"
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#include "migration/cpu.h"
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static bool vfp_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_VFP);
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}
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static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
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VMStateField *field)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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uint32_t val = qemu_get_be32(f);
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vfp_set_fpscr(env, val);
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return 0;
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}
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static int put_fpscr(QEMUFile *f, void *opaque, size_t size,
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VMStateField *field, QJSON *vmdesc)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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qemu_put_be32(f, vfp_get_fpscr(env));
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return 0;
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}
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static const VMStateInfo vmstate_fpscr = {
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.name = "fpscr",
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.get = get_fpscr,
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.put = put_fpscr,
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};
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static const VMStateDescription vmstate_vfp = {
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.name = "cpu/vfp",
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.version_id = 3,
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.minimum_version_id = 3,
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.needed = vfp_needed,
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.fields = (VMStateField[]) {
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VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
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/* The xregs array is a little awkward because element 1 (FPSCR)
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* requires a specific accessor, so we have to split it up in
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* the vmstate:
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*/
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VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
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VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
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{
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.name = "fpscr",
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.version_id = 0,
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.size = sizeof(uint32_t),
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.info = &vmstate_fpscr,
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.flags = VMS_SINGLE,
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.offset = 0,
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},
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VMSTATE_END_OF_LIST()
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}
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};
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static bool iwmmxt_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_IWMMXT);
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}
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static const VMStateDescription vmstate_iwmmxt = {
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.name = "cpu/iwmmxt",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = iwmmxt_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
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VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool m_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_M);
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}
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static const VMStateDescription vmstate_m_faultmask_primask = {
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.name = "cpu/m/faultmask-primask",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(env.v7m.faultmask, ARMCPU),
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VMSTATE_UINT32(env.v7m.primask, ARMCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_m = {
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.name = "cpu/m",
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.version_id = 4,
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.minimum_version_id = 4,
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.needed = m_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
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VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
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VMSTATE_UINT32(env.v7m.control, ARMCPU),
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VMSTATE_UINT32(env.v7m.ccr, ARMCPU),
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VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),
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VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
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VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
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VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),
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VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
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VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU),
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VMSTATE_INT32(env.v7m.exception, ARMCPU),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_m_faultmask_primask,
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NULL
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}
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};
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static bool thumb2ee_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_THUMB2EE);
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}
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static const VMStateDescription vmstate_thumb2ee = {
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.name = "cpu/thumb2ee",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = thumb2ee_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(env.teecr, ARMCPU),
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VMSTATE_UINT32(env.teehbr, ARMCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool pmsav7_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_PMSA) &&
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arm_feature(env, ARM_FEATURE_V7);
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}
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static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
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{
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ARMCPU *cpu = opaque;
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return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion;
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}
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static const VMStateDescription vmstate_pmsav7 = {
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.name = "cpu/pmsav7",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pmsav7_needed,
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.fields = (VMStateField[]) {
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VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
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vmstate_info_uint32, uint32_t),
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VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
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vmstate_info_uint32, uint32_t),
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VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
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vmstate_info_uint32, uint32_t),
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VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool pmsav7_rnr_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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/* For R profile cores pmsav7.rnr is migrated via the cpreg
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* "RGNR" definition in helper.h. For M profile we have to
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* migrate it separately.
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*/
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return arm_feature(env, ARM_FEATURE_M);
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}
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static const VMStateDescription vmstate_pmsav7_rnr = {
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.name = "cpu/pmsav7-rnr",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pmsav7_rnr_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static int get_cpsr(QEMUFile *f, void *opaque, size_t size,
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VMStateField *field)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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uint32_t val = qemu_get_be32(f);
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if (arm_feature(env, ARM_FEATURE_M)) {
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/* If the I or F bits are set then this is a migration from
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* an old QEMU which still stored the M profile FAULTMASK
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* and PRIMASK in env->daif. Set v7m.faultmask and v7m.primask
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* accordingly, and then clear the bits so they don't confuse
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* cpsr_write(). For a new QEMU, the bits here will always be
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* clear, and the data is transferred using the
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* vmstate_m_faultmask_primask subsection.
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*/
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if (val & CPSR_F) {
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env->v7m.faultmask = 1;
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}
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if (val & CPSR_I) {
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env->v7m.primask = 1;
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}
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val &= ~(CPSR_F | CPSR_I);
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}
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env->aarch64 = ((val & PSTATE_nRW) == 0);
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if (is_a64(env)) {
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pstate_write(env, val);
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return 0;
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}
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cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
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return 0;
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}
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static int put_cpsr(QEMUFile *f, void *opaque, size_t size,
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VMStateField *field, QJSON *vmdesc)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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uint32_t val;
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if (is_a64(env)) {
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val = pstate_read(env);
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} else {
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val = cpsr_read(env);
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}
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qemu_put_be32(f, val);
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return 0;
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}
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static const VMStateInfo vmstate_cpsr = {
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.name = "cpsr",
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.get = get_cpsr,
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.put = put_cpsr,
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};
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static int get_power(QEMUFile *f, void *opaque, size_t size,
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VMStateField *field)
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{
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ARMCPU *cpu = opaque;
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bool powered_off = qemu_get_byte(f);
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cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON;
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return 0;
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}
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static int put_power(QEMUFile *f, void *opaque, size_t size,
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VMStateField *field, QJSON *vmdesc)
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{
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ARMCPU *cpu = opaque;
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/* Migration should never happen while we transition power states */
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if (cpu->power_state == PSCI_ON ||
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cpu->power_state == PSCI_OFF) {
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bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false;
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qemu_put_byte(f, powered_off);
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return 0;
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} else {
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return 1;
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}
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}
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static const VMStateInfo vmstate_powered_off = {
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.name = "powered_off",
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.get = get_power,
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.put = put_power,
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};
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static void cpu_pre_save(void *opaque)
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{
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ARMCPU *cpu = opaque;
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if (kvm_enabled()) {
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if (!write_kvmstate_to_list(cpu)) {
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/* This should never fail */
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abort();
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}
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} else {
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if (!write_cpustate_to_list(cpu)) {
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/* This should never fail. */
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abort();
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}
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}
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cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
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memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
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cpu->cpreg_array_len * sizeof(uint64_t));
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memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
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cpu->cpreg_array_len * sizeof(uint64_t));
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}
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static int cpu_post_load(void *opaque, int version_id)
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{
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ARMCPU *cpu = opaque;
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int i, v;
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/* Update the values list from the incoming migration data.
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* Anything in the incoming data which we don't know about is
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* a migration failure; anything we know about but the incoming
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* data doesn't specify retains its current (reset) value.
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* The indexes list remains untouched -- we only inspect the
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* incoming migration index list so we can match the values array
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* entries with the right slots in our own values array.
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*/
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for (i = 0, v = 0; i < cpu->cpreg_array_len
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&& v < cpu->cpreg_vmstate_array_len; i++) {
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if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
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/* register in our list but not incoming : skip it */
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continue;
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}
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if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
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/* register in their list but not ours: fail migration */
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return -1;
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}
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/* matching register, copy the value over */
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cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
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v++;
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}
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if (kvm_enabled()) {
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if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
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return -1;
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}
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/* Note that it's OK for the TCG side not to know about
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* every register in the list; KVM is authoritative if
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* we're using it.
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*/
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write_list_to_cpustate(cpu);
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} else {
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if (!write_list_to_cpustate(cpu)) {
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return -1;
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}
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}
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hw_breakpoint_update_all(cpu);
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hw_watchpoint_update_all(cpu);
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return 0;
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}
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const VMStateDescription vmstate_arm_cpu = {
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.name = "cpu",
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.version_id = 22,
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.minimum_version_id = 22,
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.pre_save = cpu_pre_save,
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.post_load = cpu_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
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VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
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VMSTATE_UINT64(env.pc, ARMCPU),
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{
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.name = "cpsr",
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.version_id = 0,
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.size = sizeof(uint32_t),
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.info = &vmstate_cpsr,
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.flags = VMS_SINGLE,
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.offset = 0,
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},
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VMSTATE_UINT32(env.spsr, ARMCPU),
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VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
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VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
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VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
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VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
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VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
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VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
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VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
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/* The length-check must come before the arrays to avoid
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* incoming data possibly overflowing the array.
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*/
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VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
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VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
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cpreg_vmstate_array_len,
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0, vmstate_info_uint64, uint64_t),
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VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
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cpreg_vmstate_array_len,
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0, vmstate_info_uint64, uint64_t),
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VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
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VMSTATE_UINT64(env.exclusive_val, ARMCPU),
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VMSTATE_UINT64(env.exclusive_high, ARMCPU),
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VMSTATE_UINT64(env.features, ARMCPU),
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VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
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VMSTATE_UINT32(env.exception.fsr, ARMCPU),
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VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
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VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
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VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
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{
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.name = "power_state",
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.version_id = 0,
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.size = sizeof(bool),
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.info = &vmstate_powered_off,
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.flags = VMS_SINGLE,
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.offset = 0,
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},
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_vfp,
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&vmstate_iwmmxt,
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&vmstate_m,
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&vmstate_thumb2ee,
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/* pmsav7_rnr must come before pmsav7 so that we have the
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* region number before we test it in the VMSTATE_VALIDATE
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* in vmstate_pmsav7.
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*/
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&vmstate_pmsav7_rnr,
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&vmstate_pmsav7,
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NULL
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}
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};
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