Michael Clark e6b8552c65 SiFive RISC-V PRCI Block ... Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>		2018-03-07 08:30:28 +13:00
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riscv_hart.c	RISC-V HART Array	2018-03-07 08:30:28 +13:00
riscv_htif.c	RISC-V HTIF Console	2018-03-07 08:30:28 +13:00
sifive_clint.c	SiFive RISC-V CLINT Block	2018-03-07 08:30:28 +13:00
sifive_plic.c	SiFive RISC-V PLIC Block	2018-03-07 08:30:28 +13:00
sifive_prci.c	SiFive RISC-V PRCI Block	2018-03-07 08:30:28 +13:00
sifive_test.c	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_uart.c	SiFive RISC-V UART Device	2018-03-07 08:30:28 +13:00
spike.c	RISC-V Spike Machines	2018-03-07 08:30:28 +13:00
virt.c	RISC-V VirtIO Machine	2018-03-07 08:30:28 +13:00