Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
204 lines
6.1 KiB
C
204 lines
6.1 KiB
C
/*
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* SuperH on-chip PCIC emulation.
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*
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* Copyright (c) 2008 Takashi YOSHII
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h"
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#include "hw/sh4/sh.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "qemu/bswap.h"
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#include "exec/address-spaces.h"
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#define TYPE_SH_PCI_HOST_BRIDGE "sh_pci"
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#define SH_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(SHPCIState, (obj), TYPE_SH_PCI_HOST_BRIDGE)
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typedef struct SHPCIState {
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PCIHostState parent_obj;
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PCIDevice *dev;
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qemu_irq irq[4];
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MemoryRegion memconfig_p4;
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MemoryRegion memconfig_a7;
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MemoryRegion isa;
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uint32_t par;
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uint32_t mbr;
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uint32_t iobr;
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} SHPCIState;
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static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
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unsigned size)
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{
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SHPCIState *pcic = p;
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PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
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switch(addr) {
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case 0 ... 0xfc:
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cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
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break;
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case 0x1c0:
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pcic->par = val;
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break;
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case 0x1c4:
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pcic->mbr = val & 0xff000001;
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break;
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case 0x1c8:
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if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
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memory_region_del_subregion(get_system_memory(), &pcic->isa);
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pcic->iobr = val & 0xfffc0001;
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memory_region_add_subregion(get_system_memory(),
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pcic->iobr & 0xfffc0000, &pcic->isa);
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}
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break;
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case 0x220:
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pci_data_write(phb->bus, pcic->par, val, 4);
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break;
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}
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}
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static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
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unsigned size)
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{
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SHPCIState *pcic = p;
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PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
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switch(addr) {
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case 0 ... 0xfc:
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return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
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case 0x1c0:
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return pcic->par;
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case 0x1c4:
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return pcic->mbr;
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case 0x1c8:
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return pcic->iobr;
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case 0x220:
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return pci_data_read(phb->bus, pcic->par, 4);
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}
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return 0;
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}
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static const MemoryRegionOps sh_pci_reg_ops = {
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.read = sh_pci_reg_read,
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.write = sh_pci_reg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static int sh_pci_map_irq(PCIDevice *d, int irq_num)
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{
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return (d->devfn >> 3);
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}
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static void sh_pci_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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qemu_set_irq(pic[irq_num], level);
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}
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static int sh_pci_device_init(SysBusDevice *dev)
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{
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PCIHostState *phb;
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SHPCIState *s;
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int i;
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s = SH_PCI_HOST_BRIDGE(dev);
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phb = PCI_HOST_BRIDGE(s);
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for (i = 0; i < 4; i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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phb->bus = pci_register_bus(DEVICE(dev), "pci",
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sh_pci_set_irq, sh_pci_map_irq,
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s->irq,
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get_system_memory(),
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get_system_io(),
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PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
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memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s,
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"sh_pci", 0x224);
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memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2",
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&s->memconfig_p4, 0, 0x224);
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memory_region_init_alias(&s->isa, OBJECT(s), "sh_pci.isa",
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get_system_io(), 0, 0x40000);
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sysbus_init_mmio(dev, &s->memconfig_p4);
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sysbus_init_mmio(dev, &s->memconfig_a7);
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s->iobr = 0xfe240000;
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memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa);
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s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host");
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return 0;
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}
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static void sh_pci_host_realize(PCIDevice *d, Error **errp)
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{
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pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
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pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
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PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
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}
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static void sh_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = sh_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_HITACHI;
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k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->cannot_instantiate_with_device_add_yet = true;
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}
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static const TypeInfo sh_pci_host_info = {
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.name = "sh_pci_host",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = sh_pci_host_class_init,
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};
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static void sh_pci_device_class_init(ObjectClass *klass, void *data)
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{
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SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
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sdc->init = sh_pci_device_init;
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}
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static const TypeInfo sh_pci_device_info = {
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.name = TYPE_SH_PCI_HOST_BRIDGE,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(SHPCIState),
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.class_init = sh_pci_device_class_init,
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};
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static void sh_pci_register_types(void)
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{
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type_register_static(&sh_pci_device_info);
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type_register_static(&sh_pci_host_info);
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}
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type_init(sh_pci_register_types)
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