These are various small stylistic changes which help make things more consistent such that the automated conversion script can be simpler. It's not necessary to agree or disagree with these style changes because all of this code is going to be rewritten by the patch monkey script anyway. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
282 lines
7.9 KiB
C
282 lines
7.9 KiB
C
/*
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* QEMU IDE Emulation: PCI PIIX3/4 support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h>
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#include <hw/pc.h>
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#include <hw/pci.h>
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#include <hw/isa.h>
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#include "block.h"
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#include "sysemu.h"
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#include "dma.h"
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#include <hw/ide/pci.h>
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static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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if (size != 1) {
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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switch(addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 2:
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val = bm->status;
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break;
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default:
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val = 0xff;
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break;
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}
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#ifdef DEBUG_IDE
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printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void bmdma_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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BMDMAState *bm = opaque;
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if (size != 1) {
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return;
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}
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#ifdef DEBUG_IDE
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printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
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#endif
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switch(addr & 3) {
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case 0:
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return bmdma_cmd_writeb(bm, val);
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case 2:
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
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break;
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}
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}
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static MemoryRegionOps piix_bmdma_ops = {
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.read = bmdma_read,
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.write = bmdma_write,
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};
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static void bmdma_setup_bar(PCIIDEState *d)
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{
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int i;
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memory_region_init(&d->bmdma_bar, "piix-bmdma-container", 16);
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for(i = 0;i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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memory_region_init_io(&bm->extra_io, &piix_bmdma_ops, bm,
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"piix-bmdma", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
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memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
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"bmdma", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
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}
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}
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static void piix3_reset(void *opaque)
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{
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PCIIDEState *d = opaque;
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uint8_t *pci_conf = d->dev.config;
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int i;
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for (i = 0; i < 2; i++) {
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ide_bus_reset(&d->bus[i]);
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}
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/* TODO: this is the default. do not override. */
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pci_conf[PCI_COMMAND] = 0x00;
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/* TODO: this is the default. do not override. */
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pci_conf[PCI_COMMAND + 1] = 0x00;
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/* TODO: use pci_set_word */
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pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
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pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
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pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
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}
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static void pci_piix_init_ports(PCIIDEState *d) {
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static const struct {
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int iobase;
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int iobase2;
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int isairq;
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} port_info[] = {
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{0x1f0, 0x3f6, 14},
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{0x170, 0x376, 15},
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};
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int i;
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for (i = 0; i < 2; i++) {
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ide_bus_new(&d->bus[i], &d->dev.qdev, i);
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ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
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port_info[i].iobase2);
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ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
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bmdma_init(&d->bus[i], &d->bmdma[i], d);
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d->bmdma[i].bus = &d->bus[i];
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qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
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&d->bmdma[i].dma);
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}
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}
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static int pci_piix_ide_initfn(PCIDevice *dev)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
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uint8_t *pci_conf = d->dev.config;
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pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
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qemu_register_reset(piix3_reset, d);
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bmdma_setup_bar(d);
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pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
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vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
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pci_piix_init_ports(d);
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return 0;
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}
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static int pci_piix3_xen_ide_unplug(DeviceState *dev)
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{
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PCIDevice *pci_dev;
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PCIIDEState *pci_ide;
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DriveInfo *di;
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int i = 0;
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pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
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pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);
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for (; i < 3; i++) {
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di = drive_get_by_index(IF_IDE, i);
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if (di != NULL && !di->media_cd) {
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DeviceState *ds = bdrv_get_attached_dev(di->bdrv);
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if (ds) {
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bdrv_detach_dev(di->bdrv, ds);
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}
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bdrv_close(di->bdrv);
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pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
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drive_put_ref(di);
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}
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}
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qdev_reset_all(&(pci_ide->dev.qdev));
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return 0;
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}
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PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
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pci_ide_create_devs(dev, hd_table);
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return dev;
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}
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static int pci_piix_ide_exitfn(PCIDevice *dev)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
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unsigned i;
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for (i = 0; i < 2; ++i) {
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
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memory_region_destroy(&d->bmdma[i].extra_io);
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
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memory_region_destroy(&d->bmdma[i].addr_ioport);
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}
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memory_region_destroy(&d->bmdma_bar);
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return 0;
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}
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/* hd_table must contain 4 block drivers */
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/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
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PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create_simple(bus, devfn, "piix3-ide");
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pci_ide_create_devs(dev, hd_table);
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return dev;
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}
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/* hd_table must contain 4 block drivers */
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/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
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PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create_simple(bus, devfn, "piix4-ide");
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pci_ide_create_devs(dev, hd_table);
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return dev;
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}
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static PCIDeviceInfo piix3_ide_info = {
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.qdev.name = "piix3-ide",
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.qdev.size = sizeof(PCIIDEState),
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.qdev.no_user = 1,
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.no_hotplug = 1,
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.init = pci_piix_ide_initfn,
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.exit = pci_piix_ide_exitfn,
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.vendor_id = PCI_VENDOR_ID_INTEL,
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.device_id = PCI_DEVICE_ID_INTEL_82371SB_1,
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.class_id = PCI_CLASS_STORAGE_IDE,
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};
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static PCIDeviceInfo piix3_ide_xen_info = {
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.qdev.name = "piix3-ide-xen",
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.qdev.size = sizeof(PCIIDEState),
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.qdev.no_user = 1,
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.qdev.unplug = pci_piix3_xen_ide_unplug,
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.init = pci_piix_ide_initfn,
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.vendor_id = PCI_VENDOR_ID_INTEL,
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.device_id = PCI_DEVICE_ID_INTEL_82371SB_1,
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.class_id = PCI_CLASS_STORAGE_IDE,
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};
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static PCIDeviceInfo piix4_ide_info = {
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.qdev.name = "piix4-ide",
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.qdev.size = sizeof(PCIIDEState),
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.qdev.no_user = 1,
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.no_hotplug = 1,
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.init = pci_piix_ide_initfn,
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.exit = pci_piix_ide_exitfn,
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.vendor_id = PCI_VENDOR_ID_INTEL,
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.device_id = PCI_DEVICE_ID_INTEL_82371AB,
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.class_id = PCI_CLASS_STORAGE_IDE,
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};
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static void piix_ide_register(void)
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{
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pci_qdev_register(&piix3_ide_info);
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pci_qdev_register(&piix3_ide_xen_info);
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pci_qdev_register(&piix4_ide_info);
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}
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device_init(piix_ide_register);
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