37e33be7ea
At present, when booting U-Boot on QEMU sabrelite, we see: Net: Board Net Initialization Failed No ethernet found. U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real board, the Ethernet PHY is at address 6. Adjust this by updating the "fec-phy-num" property of the fsl_imx6 SoC object. With this change, U-Boot sees the PHY but complains MAC address: Net: using phy at 6 FEC [PRIME] Error: FEC address not set. This is due to U-Boot tries to read the MAC address from the fuse, which QEMU does not have any valid content filled in. However this does not prevent the Ethernet from working in QEMU. We just need to set up the MAC address later in the U-Boot command shell, by: => setenv ethaddr 00:11:22:33:44:55 Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20210106063504.10841-4-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
117 lines
3.7 KiB
C
117 lines
3.7 KiB
C
/*
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* SABRELITE Board System emulation.
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*
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* Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This code is licensed under the GPL, version 2 or later.
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* See the file `COPYING' in the top level directory.
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*
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* It (partially) emulates a sabrelite board, with a Freescale
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* i.MX6 SoC
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/arm/fsl-imx6.h"
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#include "hw/boards.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/sysemu.h"
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#include "qemu/error-report.h"
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#include "sysemu/qtest.h"
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static struct arm_boot_info sabrelite_binfo = {
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/* DDR memory start */
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.loader_start = FSL_IMX6_MMDC_ADDR,
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/* No board ID, we boot from DT tree */
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.board_id = -1,
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};
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/* No need to do any particular setup for secondary boot */
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static void sabrelite_write_secondary(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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}
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/* Secondary cores are reset through SRC device */
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static void sabrelite_reset_secondary(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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}
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static void sabrelite_init(MachineState *machine)
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{
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FslIMX6State *s;
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/* Check the amount of memory is compatible with the SOC */
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if (machine->ram_size > FSL_IMX6_MMDC_SIZE) {
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error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
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machine->ram_size, FSL_IMX6_MMDC_SIZE);
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exit(1);
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}
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s = FSL_IMX6(object_new(TYPE_FSL_IMX6));
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object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
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/* Ethernet PHY address is 6 */
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object_property_set_int(OBJECT(s), "fec-phy-num", 6, &error_fatal);
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qdev_realize(DEVICE(s), NULL, &error_fatal);
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memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
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machine->ram);
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{
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/*
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* TODO: Ideally we would expose the chip select and spi bus on the
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* SoC object using alias properties; then we would not need to
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* directly access the underlying spi device object.
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*/
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/* Add the sst25vf016b NOR FLASH memory to first SPI */
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Object *spi_dev;
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spi_dev = object_resolve_path_component(OBJECT(s), "spi1");
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if (spi_dev) {
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SSIBus *spi_bus;
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spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi");
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if (spi_bus) {
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DeviceState *flash_dev;
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qemu_irq cs_line;
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DriveInfo *dinfo = drive_get_next(IF_MTD);
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flash_dev = qdev_new("sst25vf016b");
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if (dinfo) {
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qdev_prop_set_drive_err(flash_dev, "drive",
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blk_by_legacy_dinfo(dinfo),
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&error_fatal);
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}
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qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal);
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cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
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sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
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}
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}
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}
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sabrelite_binfo.ram_size = machine->ram_size;
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sabrelite_binfo.nb_cpus = machine->smp.cpus;
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sabrelite_binfo.secure_boot = true;
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sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
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sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
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if (!qtest_enabled()) {
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arm_load_kernel(&s->cpu[0], machine, &sabrelite_binfo);
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}
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}
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static void sabrelite_machine_init(MachineClass *mc)
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{
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mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)";
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mc->init = sabrelite_init;
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mc->max_cpus = FSL_IMX6_NUM_CPUS;
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mc->ignore_memory_transaction_failures = true;
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mc->default_ram_id = "sabrelite.ram";
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}
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DEFINE_MACHINE("sabrelite", sabrelite_machine_init)
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