This patch adds support for writing misa. misa is validated based on rules in the ISA specification. 'E' is mutually exclusive with all other extensions. 'D' depends on 'F' so 'D' bit is dropped if 'F' is not present. A conservative approach to consistency is taken by flushing the translation cache on misa writes. misa_mask is added to the CPU struct to store the original set of extensions. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
331 lines
9.9 KiB
C
331 lines
9.9 KiB
C
/*
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* QEMU RISC-V CPU
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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/* QEMU addressing/paging config */
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#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
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#if defined(TARGET_RISCV64)
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#define TARGET_LONG_BITS 64
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#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
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#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
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#elif defined(TARGET_RISCV32)
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#define TARGET_LONG_BITS 32
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#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
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#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
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#endif
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#define TCG_GUEST_DEFAULT_MO 0
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#define CPUArchState struct CPURISCVState
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#include "qemu-common.h"
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#include "qom/cpu.h"
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat.h"
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#define TYPE_RISCV_CPU "riscv-cpu"
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#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
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#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
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#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
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#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
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#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
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#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
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#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
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#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
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#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
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#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
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#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
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#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
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#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
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#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
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#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
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#if defined(TARGET_RISCV32)
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#define RVXLEN RV32
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#elif defined(TARGET_RISCV64)
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#define RVXLEN RV64
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#endif
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#define RV(x) ((target_ulong)1 << (x - 'A'))
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#define RVI RV('I')
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#define RVE RV('E') /* E and I are mutually exclusive */
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#define RVM RV('M')
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#define RVA RV('A')
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#define RVF RV('F')
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#define RVD RV('D')
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#define RVC RV('C')
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#define RVS RV('S')
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#define RVU RV('U')
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/* S extension denotes that Supervisor mode exists, however it is possible
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to have a core that support S mode but does not have an MMU and there
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is currently no bit in misa to indicate whether an MMU exists or not
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so a cpu features bitfield is required, likewise for optional PMP support */
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enum {
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RISCV_FEATURE_MMU,
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RISCV_FEATURE_PMP,
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RISCV_FEATURE_MISA
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};
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#define USER_VERSION_2_02_0 0x00020200
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#define PRIV_VERSION_1_09_1 0x00010901
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#define PRIV_VERSION_1_10_0 0x00011000
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#define TRANSLATE_FAIL 1
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#define TRANSLATE_SUCCESS 0
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#define NB_MMU_MODES 4
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#define MMU_USER_IDX 3
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#define MAX_RISCV_PMPS (16)
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typedef struct CPURISCVState CPURISCVState;
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#include "pmp.h"
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struct CPURISCVState {
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target_ulong gpr[32];
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uint64_t fpr[32]; /* assume both F and D extensions */
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target_ulong pc;
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target_ulong load_res;
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target_ulong load_val;
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target_ulong frm;
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target_ulong badaddr;
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target_ulong user_ver;
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target_ulong priv_ver;
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target_ulong misa;
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target_ulong misa_mask;
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uint32_t features;
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#ifndef CONFIG_USER_ONLY
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target_ulong priv;
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target_ulong resetvec;
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target_ulong mhartid;
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target_ulong mstatus;
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/*
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* CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
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* by I/O threads. It should be read with atomic_read. It should be updated
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* using riscv_cpu_update_mip with the iothread mutex held. The iothread
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* mutex must be held because mip must be consistent with the CPU inturrept
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* state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt
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* wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
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* mip is 32-bits to allow atomic_read on 32-bit hosts.
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*/
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uint32_t mip;
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target_ulong mie;
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target_ulong mideleg;
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target_ulong sptbr; /* until: priv-1.9.1 */
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target_ulong satp; /* since: priv-1.10.0 */
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target_ulong sbadaddr;
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target_ulong mbadaddr;
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target_ulong medeleg;
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target_ulong stvec;
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target_ulong sepc;
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target_ulong scause;
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target_ulong mtvec;
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target_ulong mepc;
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target_ulong mcause;
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target_ulong mtval; /* since: priv-1.10.0 */
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target_ulong scounteren;
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target_ulong mcounteren;
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target_ulong sscratch;
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target_ulong mscratch;
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/* temporary htif regs */
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uint64_t mfromhost;
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uint64_t mtohost;
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uint64_t timecmp;
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/* physical memory protection */
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pmp_table_t pmp_state;
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#endif
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float_status fp_status;
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/* QEMU */
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CPU_COMMON
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/* Fields from here on are preserved across CPU reset. */
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QEMUTimer *timer; /* Internal timer */
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};
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#define RISCV_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
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#define RISCV_CPU(obj) \
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OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
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#define RISCV_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
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/**
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* RISCVCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A RISCV CPU model.
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*/
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typedef struct RISCVCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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void (*parent_reset)(CPUState *cpu);
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} RISCVCPUClass;
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/**
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* RISCVCPU:
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* @env: #CPURISCVState
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*
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* A RISCV CPU.
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*/
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typedef struct RISCVCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPURISCVState env;
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} RISCVCPU;
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static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env)
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{
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return container_of(env, RISCVCPU, env);
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}
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static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
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{
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return (env->misa & ext) != 0;
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}
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static inline bool riscv_feature(CPURISCVState *env, int feature)
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{
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return env->features & (1ULL << feature);
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}
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#include "cpu_user.h"
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#include "cpu_bits.h"
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extern const char * const riscv_int_regnames[];
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extern const char * const riscv_fpr_regnames[];
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extern const char * const riscv_excp_names[];
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extern const char * const riscv_intr_names[];
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#define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e))
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#define ENV_OFFSET offsetof(RISCVCPU, env)
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void riscv_cpu_do_interrupt(CPUState *cpu);
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int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
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int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
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hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr);
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int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
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int rw, int mmu_idx);
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char *riscv_isa_string(RISCVCPU *cpu);
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void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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#define cpu_signal_handler riscv_cpu_signal_handler
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#define cpu_list riscv_cpu_list
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#define cpu_mmu_index riscv_cpu_mmu_index
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#ifndef CONFIG_USER_ONLY
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uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
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#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
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#endif
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void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
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void riscv_translate_init(void);
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int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
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void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
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uint32_t exception, uintptr_t pc);
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target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
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void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
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#define TB_FLAGS_MMU_MASK 3
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#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
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static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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#ifdef CONFIG_USER_ONLY
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*flags = TB_FLAGS_MSTATUS_FS;
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#else
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*flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
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#endif
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}
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int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask);
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static inline void riscv_csr_write(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
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}
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static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
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{
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target_ulong val = 0;
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riscv_csrrw(env, csrno, &val, 0, 0);
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return val;
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}
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typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
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typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
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target_ulong *ret_value);
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typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
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target_ulong new_value);
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typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
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target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
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typedef struct {
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riscv_csr_predicate_fn predicate;
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riscv_csr_read_fn read;
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riscv_csr_write_fn write;
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riscv_csr_op_fn op;
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} riscv_csr_operations;
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void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
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void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
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#include "exec/cpu-all.h"
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#endif /* RISCV_CPU_H */
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