This is the same transformation as in the previous commit, except sysbus_init_child_obj() and realize are too separated for the commit's Coccinelle script to handle, typically because sysbus_init_child_obj() is in a device's instance_init() method, and the matching realize is in its realize() method. Perhaps a Coccinelle wizard could make it transform that pattern, but I'm just a bungler, and the best I can do is transforming the two separate parts separately: @@ expression errp; expression child; symbol true; @@ - object_property_set_bool(OBJECT(child), true, "realized", errp); + sysbus_realize(SYS_BUS_DEVICE(child), errp); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression errp; expression child; symbol true; @@ - object_property_set_bool(child, true, "realized", errp); + sysbus_realize(SYS_BUS_DEVICE(child), errp); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; @@ - qdev_init_nofail(DEVICE(child)); + sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; expression dev; @@ dev = DEVICE(child); ... - qdev_init_nofail(dev); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; identifier dev; @@ DeviceState *dev = DEVICE(child); ... - qdev_init_nofail(dev); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression parent, name, size, type; expression child; symbol true; @@ - sysbus_init_child_obj(parent, name, child, size, type); + sysbus_init_child_XXX(parent, name, child, size, type); @@ expression parent, propname, type; expression child; @@ - sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type) + object_initialize_child(parent, propname, child, type) @@ expression parent, propname, type; expression child; @@ - sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type) + object_initialize_child(parent, propname, &child, type) This script is *unsound*: we need to manually verify init and realize conversions are properly paired. This commit has only the pairs where object_initialize_child()'s @child and sysbus_realize()'s @dev argument text match exactly within the same source file. Note that Coccinelle chokes on ARMSSE typedef vs. macro in hw/arm/armsse.c. Worked around by temporarily renaming the macro for the spatch run. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
299 lines
12 KiB
C
299 lines
12 KiB
C
/*
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* STM32F405 SoC
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "hw/arm/stm32f405_soc.h"
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#include "hw/misc/unimp.h"
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#define SYSCFG_ADD 0x40013800
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static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
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0x40004C00, 0x40005000, 0x40011400,
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0x40007800, 0x40007C00 };
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/* At the moment only Timer 2 to 5 are modelled */
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static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
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0x40000800, 0x40000C00 };
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static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
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0x40012300, 0x40012400, 0x40012500 };
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static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
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0x40013400, 0x40015000, 0x40015400 };
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#define EXTI_ADDR 0x40013C00
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#define SYSCFG_IRQ 71
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static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 };
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static const int timer_irq[] = { 28, 29, 30, 50 };
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#define ADC_IRQ 18
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static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 };
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static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
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40, 40, 40, 40, 40} ;
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static void stm32f405_soc_initfn(Object *obj)
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{
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STM32F405State *s = STM32F405_SOC(obj);
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int i;
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object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
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object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG);
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for (i = 0; i < STM_NUM_USARTS; i++) {
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object_initialize_child(obj, "usart[*]", &s->usart[i],
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TYPE_STM32F2XX_USART);
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}
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for (i = 0; i < STM_NUM_TIMERS; i++) {
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object_initialize_child(obj, "timer[*]", &s->timer[i],
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TYPE_STM32F2XX_TIMER);
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}
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for (i = 0; i < STM_NUM_ADCS; i++) {
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object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
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}
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for (i = 0; i < STM_NUM_SPIS; i++) {
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object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
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}
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object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
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}
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static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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STM32F405State *s = STM32F405_SOC(dev_soc);
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MemoryRegion *system_memory = get_system_memory();
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DeviceState *dev, *armv7m;
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SysBusDevice *busdev;
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Error *err = NULL;
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int i;
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memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash",
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FLASH_SIZE, &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
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"STM32F405.flash.alias", &s->flash, 0,
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FLASH_SIZE);
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memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
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memory_region_add_subregion(system_memory, 0, &s->flash_alias);
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memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,
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&err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
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armv7m = DEVICE(&s->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 96);
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qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
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qdev_prop_set_bit(armv7m, "enable-bitband", true);
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object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory),
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"memory", &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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/* System configuration controller */
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dev = DEVICE(&s->syscfg);
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sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
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/* Attach UART (uses USART registers) and USART controllers */
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for (i = 0; i < STM_NUM_USARTS; i++) {
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dev = DEVICE(&(s->usart[i]));
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qdev_prop_set_chr(dev, "chardev", serial_hd(i));
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sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, usart_addr[i]);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
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}
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/* Timer 2 to 5 */
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for (i = 0; i < STM_NUM_TIMERS; i++) {
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dev = DEVICE(&(s->timer[i]));
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qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
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sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, timer_addr[i]);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
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}
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/* ADC device, the IRQs are ORed together */
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object_initialize_child_with_props(OBJECT(s), "adc-orirq", &s->adc_irqs,
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sizeof(s->adc_irqs), TYPE_OR_IRQ, &err,
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NULL);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS,
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"num-lines", &err);
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object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
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qdev_get_gpio_in(armv7m, ADC_IRQ));
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for (i = 0; i < STM_NUM_ADCS; i++) {
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dev = DEVICE(&(s->adc[i]));
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sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, adc_addr[i]);
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sysbus_connect_irq(busdev, 0,
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qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
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}
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/* SPI devices */
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for (i = 0; i < STM_NUM_SPIS; i++) {
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dev = DEVICE(&(s->spi[i]));
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sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, spi_addr[i]);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
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}
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/* EXTI device */
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dev = DEVICE(&s->exti);
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sysbus_realize(SYS_BUS_DEVICE(&s->exti), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, EXTI_ADDR);
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for (i = 0; i < 16; i++) {
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sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
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}
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for (i = 0; i < 16; i++) {
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qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
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}
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create_unimplemented_device("timer[7]", 0x40001400, 0x400);
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create_unimplemented_device("timer[12]", 0x40001800, 0x400);
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create_unimplemented_device("timer[6]", 0x40001000, 0x400);
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create_unimplemented_device("timer[13]", 0x40001C00, 0x400);
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create_unimplemented_device("timer[14]", 0x40002000, 0x400);
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create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);
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create_unimplemented_device("WWDG", 0x40002C00, 0x400);
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create_unimplemented_device("IWDG", 0x40003000, 0x400);
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create_unimplemented_device("I2S2ext", 0x40003000, 0x400);
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create_unimplemented_device("I2S3ext", 0x40004000, 0x400);
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create_unimplemented_device("I2C1", 0x40005400, 0x400);
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create_unimplemented_device("I2C2", 0x40005800, 0x400);
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create_unimplemented_device("I2C3", 0x40005C00, 0x400);
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create_unimplemented_device("CAN1", 0x40006400, 0x400);
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create_unimplemented_device("CAN2", 0x40006800, 0x400);
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create_unimplemented_device("PWR", 0x40007000, 0x400);
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create_unimplemented_device("DAC", 0x40007400, 0x400);
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create_unimplemented_device("timer[1]", 0x40010000, 0x400);
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create_unimplemented_device("timer[8]", 0x40010400, 0x400);
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create_unimplemented_device("SDIO", 0x40012C00, 0x400);
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create_unimplemented_device("timer[9]", 0x40014000, 0x400);
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create_unimplemented_device("timer[10]", 0x40014400, 0x400);
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create_unimplemented_device("timer[11]", 0x40014800, 0x400);
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create_unimplemented_device("GPIOA", 0x40020000, 0x400);
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create_unimplemented_device("GPIOB", 0x40020400, 0x400);
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create_unimplemented_device("GPIOC", 0x40020800, 0x400);
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create_unimplemented_device("GPIOD", 0x40020C00, 0x400);
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create_unimplemented_device("GPIOE", 0x40021000, 0x400);
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create_unimplemented_device("GPIOF", 0x40021400, 0x400);
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create_unimplemented_device("GPIOG", 0x40021800, 0x400);
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create_unimplemented_device("GPIOH", 0x40021C00, 0x400);
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create_unimplemented_device("GPIOI", 0x40022000, 0x400);
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create_unimplemented_device("CRC", 0x40023000, 0x400);
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create_unimplemented_device("RCC", 0x40023800, 0x400);
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create_unimplemented_device("Flash Int", 0x40023C00, 0x400);
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create_unimplemented_device("BKPSRAM", 0x40024000, 0x400);
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create_unimplemented_device("DMA1", 0x40026000, 0x400);
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create_unimplemented_device("DMA2", 0x40026400, 0x400);
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create_unimplemented_device("Ethernet", 0x40028000, 0x1400);
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create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000);
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create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000);
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create_unimplemented_device("DCMI", 0x50050000, 0x400);
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create_unimplemented_device("RNG", 0x50060800, 0x400);
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}
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static Property stm32f405_soc_properties[] = {
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DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = stm32f405_soc_realize;
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device_class_set_props(dc, stm32f405_soc_properties);
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/* No vmstate or reset required: device has no internal state */
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}
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static const TypeInfo stm32f405_soc_info = {
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.name = TYPE_STM32F405_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(STM32F405State),
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.instance_init = stm32f405_soc_initfn,
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.class_init = stm32f405_soc_class_init,
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};
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static void stm32f405_soc_types(void)
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{
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type_register_static(&stm32f405_soc_info);
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}
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type_init(stm32f405_soc_types)
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