There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023122913.19561-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
267 lines
8.7 KiB
C
267 lines
8.7 KiB
C
/*
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* KVM-based ITS implementation for a GICv3-based system
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Written by Pavel Fedin <p.fedin@samsung.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/intc/arm_gicv3_its_common.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/runstate.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#include "migration/blocker.h"
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#include "qom/object.h"
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#define TYPE_KVM_ARM_ITS "arm-its-kvm"
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typedef struct KVMARMITSClass KVMARMITSClass;
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/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
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DECLARE_OBJ_CHECKERS(GICv3ITSState, KVMARMITSClass,
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KVM_ARM_ITS, TYPE_KVM_ARM_ITS)
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struct KVMARMITSClass {
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GICv3ITSCommonClass parent_class;
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void (*parent_reset)(DeviceState *dev);
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};
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static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
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{
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struct kvm_msi msi;
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if (unlikely(!s->translater_gpa_known)) {
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MemoryRegion *mr = &s->iomem_its_translation;
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MemoryRegionSection mrs;
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mrs = memory_region_find(mr, 0, 1);
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memory_region_unref(mrs.mr);
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s->gits_translater_gpa = mrs.offset_within_address_space + 0x40;
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s->translater_gpa_known = true;
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}
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msi.address_lo = extract64(s->gits_translater_gpa, 0, 32);
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msi.address_hi = extract64(s->gits_translater_gpa, 32, 32);
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msi.data = le32_to_cpu(value);
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msi.flags = KVM_MSI_VALID_DEVID;
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msi.devid = devid;
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memset(msi.pad, 0, sizeof(msi.pad));
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return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
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}
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/**
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* vm_change_state_handler - VM change state callback aiming at flushing
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* ITS tables into guest RAM
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*
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* The tables get flushed to guest RAM whenever the VM gets stopped.
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*/
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static void vm_change_state_handler(void *opaque, int running,
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RunState state)
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{
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GICv3ITSState *s = (GICv3ITSState *)opaque;
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Error *err = NULL;
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if (running) {
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return;
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}
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
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KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err);
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if (err) {
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error_report_err(err);
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}
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}
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static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
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{
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GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
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s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false);
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if (s->dev_fd < 0) {
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error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS");
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return;
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}
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/* explicit init of the ITS */
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
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KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort);
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/* register the base address */
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kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
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KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd, 0);
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gicv3_its_init_mmio(s, NULL);
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if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CTLR)) {
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error_setg(&s->migration_blocker, "This operating system kernel "
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"does not support vITS migration");
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if (migrate_add_blocker(s->migration_blocker, errp) < 0) {
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error_free(s->migration_blocker);
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return;
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}
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} else {
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qemu_add_vm_change_state_handler(vm_change_state_handler, s);
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}
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kvm_msi_use_devid = true;
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kvm_gsi_direct_mapping = false;
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kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
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}
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/**
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* kvm_arm_its_pre_save - handles the saving of ITS registers.
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* ITS tables are flushed into guest RAM separately and earlier,
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* through the VM change state handler, since at the moment pre_save()
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* is called, the guest RAM has already been saved.
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*/
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static void kvm_arm_its_pre_save(GICv3ITSState *s)
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{
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int i;
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for (i = 0; i < 8; i++) {
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_BASER + i * 8, &s->baser[i], false,
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&error_abort);
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}
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CTLR, &s->ctlr, false, &error_abort);
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CBASER, &s->cbaser, false, &error_abort);
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CREADR, &s->creadr, false, &error_abort);
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CWRITER, &s->cwriter, false, &error_abort);
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_IIDR, &s->iidr, false, &error_abort);
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}
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/**
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* kvm_arm_its_post_load - Restore both the ITS registers and tables
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*/
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static void kvm_arm_its_post_load(GICv3ITSState *s)
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{
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int i;
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_IIDR, &s->iidr, true, &error_abort);
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/*
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* must be written before GITS_CREADR since GITS_CBASER write
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* access resets GITS_CREADR.
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*/
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CBASER, &s->cbaser, true, &error_abort);
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CREADR, &s->creadr, true, &error_abort);
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CWRITER, &s->cwriter, true, &error_abort);
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for (i = 0; i < 8; i++) {
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_BASER + i * 8, &s->baser[i], true,
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&error_abort);
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}
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
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KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true,
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&error_abort);
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CTLR, &s->ctlr, true, &error_abort);
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}
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static void kvm_arm_its_reset(DeviceState *dev)
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{
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GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
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KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
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int i;
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c->parent_reset(dev);
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if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
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KVM_DEV_ARM_ITS_CTRL_RESET)) {
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
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KVM_DEV_ARM_ITS_CTRL_RESET, NULL, true, &error_abort);
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return;
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}
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warn_report("ITS KVM: full reset is not supported by the host kernel");
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if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CTLR)) {
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return;
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}
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CTLR, &s->ctlr, true, &error_abort);
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_CBASER, &s->cbaser, true, &error_abort);
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for (i = 0; i < 8; i++) {
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
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GITS_BASER + i * 8, &s->baser[i], true,
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&error_abort);
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}
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}
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static Property kvm_arm_its_props[] = {
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DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3",
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GICv3State *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
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KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass);
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dc->realize = kvm_arm_its_realize;
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device_class_set_props(dc, kvm_arm_its_props);
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device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
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icc->send_msi = kvm_its_send_msi;
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icc->pre_save = kvm_arm_its_pre_save;
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icc->post_load = kvm_arm_its_post_load;
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}
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static const TypeInfo kvm_arm_its_info = {
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.name = TYPE_KVM_ARM_ITS,
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.parent = TYPE_ARM_GICV3_ITS_COMMON,
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.instance_size = sizeof(GICv3ITSState),
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.class_init = kvm_arm_its_class_init,
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.class_size = sizeof(KVMARMITSClass),
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};
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static void kvm_arm_its_register_types(void)
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{
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type_register_static(&kvm_arm_its_info);
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}
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type_init(kvm_arm_its_register_types)
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