The openrisc code uses an old style of interrupt handling, where a separate standalone set of qemu_irqs invoke a function openrisc_pic_cpu_handler() which signals the interrupt to the CPU proper by directly calling cpu_interrupt() and cpu_reset_interrupt(). Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, and the neater modern way to implement this is to simply have the CPU object itself provide the input IRQ lines. Create GPIO inputs to the OpenRISC CPU object, and make the only user of cpu_openrisc_pic_init() wire up directly to those instead. This allows us to delete the hw/openrisc/pic_cpu.c file entirely. This fixes a trivial memory leak reported by Coverity of the IRQs allocated in cpu_openrisc_pic_init(). Fixes: Coverity CID 1421934 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stafford Horne <shorne@gmail.com> Message-id: 20201127225127.14770-4-peter.maydell@linaro.org
197 lines
5.9 KiB
C
197 lines
5.9 KiB
C
/*
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* OpenRISC simulator for use as an IIS.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Feng Gao <gf91597@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/irq.h"
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#include "hw/boards.h"
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#include "elf.h"
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#include "hw/char/serial.h"
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#include "net/net.h"
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#include "hw/loader.h"
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#include "hw/qdev-properties.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "hw/sysbus.h"
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#include "sysemu/qtest.h"
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#include "sysemu/reset.h"
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#include "hw/core/split-irq.h"
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#define KERNEL_LOAD_ADDR 0x100
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static struct openrisc_boot_info {
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uint32_t bootstrap_pc;
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} boot_info;
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static void main_cpu_reset(void *opaque)
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{
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OpenRISCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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cpu_reset(CPU(cpu));
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cpu_set_pc(cs, boot_info.bootstrap_pc);
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}
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static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
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{
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return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
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}
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static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,
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int num_cpus, OpenRISCCPU *cpus[],
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int irq_pin, NICInfo *nd)
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{
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DeviceState *dev;
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SysBusDevice *s;
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int i;
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dev = qdev_new("open_eth");
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qdev_set_nic_properties(dev, nd);
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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if (num_cpus > 1) {
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DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
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qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
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qdev_realize_and_unref(splitter, NULL, &error_fatal);
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for (i = 0; i < num_cpus; i++) {
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qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
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}
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sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0));
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} else {
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sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin));
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}
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sysbus_mmio_map(s, 0, base);
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sysbus_mmio_map(s, 1, descriptors);
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}
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static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,
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OpenRISCCPU *cpus[], int irq_pin)
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{
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DeviceState *dev;
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SysBusDevice *s;
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int i;
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dev = qdev_new("or1k-ompic");
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qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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for (i = 0; i < num_cpus; i++) {
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sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
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}
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sysbus_mmio_map(s, 0, base);
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}
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static void openrisc_load_kernel(ram_addr_t ram_size,
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const char *kernel_filename)
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{
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long kernel_size;
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uint64_t elf_entry;
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hwaddr entry;
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if (kernel_filename && !qtest_enabled()) {
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kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
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&elf_entry, NULL, NULL, NULL, 1, EM_OPENRISC,
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1, 0);
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entry = elf_entry;
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if (kernel_size < 0) {
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kernel_size = load_uimage(kernel_filename,
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&entry, NULL, NULL, NULL, NULL);
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}
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if (kernel_size < 0) {
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kernel_size = load_image_targphys(kernel_filename,
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KERNEL_LOAD_ADDR,
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ram_size - KERNEL_LOAD_ADDR);
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}
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if (entry <= 0) {
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entry = KERNEL_LOAD_ADDR;
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}
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if (kernel_size < 0) {
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error_report("couldn't load the kernel '%s'", kernel_filename);
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exit(1);
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}
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boot_info.bootstrap_pc = entry;
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}
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}
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static void openrisc_sim_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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const char *kernel_filename = machine->kernel_filename;
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OpenRISCCPU *cpus[2] = {};
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MemoryRegion *ram;
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qemu_irq serial_irq;
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int n;
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unsigned int smp_cpus = machine->smp.cpus;
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assert(smp_cpus >= 1 && smp_cpus <= 2);
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for (n = 0; n < smp_cpus; n++) {
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cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
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if (cpus[n] == NULL) {
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fprintf(stderr, "Unable to find CPU definition!\n");
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exit(1);
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}
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cpu_openrisc_clock_init(cpus[n]);
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qemu_register_reset(main_cpu_reset, cpus[n]);
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}
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ram = g_malloc(sizeof(*ram));
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memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
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memory_region_add_subregion(get_system_memory(), 0, ram);
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if (nd_table[0].used) {
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openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus,
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cpus, 4, nd_table);
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}
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if (smp_cpus > 1) {
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openrisc_sim_ompic_init(0x98000000, smp_cpus, cpus, 1);
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serial_irq = qemu_irq_split(get_cpu_irq(cpus, 0, 2),
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get_cpu_irq(cpus, 1, 2));
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} else {
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serial_irq = get_cpu_irq(cpus, 0, 2);
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}
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serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,
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115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
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openrisc_load_kernel(ram_size, kernel_filename);
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}
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static void openrisc_sim_machine_init(MachineClass *mc)
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{
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mc->desc = "or1k simulation";
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mc->init = openrisc_sim_init;
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mc->max_cpus = 2;
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mc->is_default = true;
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mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
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}
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DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)
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