Present code uses @size==UINT64_MAX to initialize IOMMU. It infers that it can map any 64-bit IOVA whatsoever. But in fact, the largest DMA range for each PCI Device on s390x is from ZPCI_SDMA_ADDR to ZPCI_EDMA_ADDR. The largest value is returned from hardware, which is to indicate the largest range hardware can support. But the real IOMMU size for specific PCI Device is obtained once qemu intercepts mpcifc instruction that guest is requesting a DMA range for that PCI Device. Therefore, before intercepting mpcifc instruction, qemu cannot be aware of the size of IOMMU region that guest will use. Moreover, iommu replay during device initialization for the whole region in 4k steps takes a very long time. In conclusion, this patch intializes IOMMU region for each PCI Device when intercept mpcifc instruction which is to register DMA range for the PCI Device. And then, destroy IOMMU region when guest wants to deregister IOAT. Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
619 lines
17 KiB
C
619 lines
17 KiB
C
/*
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* s390 PCI BUS
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*
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* Copyright 2014 IBM Corp.
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* Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
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* Hong Bo Li <lihbbj@cn.ibm.com>
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* Yi Min Zhao <zyimin@cn.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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#include "s390-pci-bus.h"
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#include <hw/pci/pci_bus.h>
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#include <hw/pci/msi.h>
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#include <qemu/error-report.h>
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/* #define DEBUG_S390PCI_BUS */
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#ifdef DEBUG_S390PCI_BUS
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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int chsc_sei_nt2_get_event(void *res)
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{
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ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
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PciCcdfAvail *accdf;
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PciCcdfErr *eccdf;
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int rc = 1;
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SeiContainer *sei_cont;
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return rc;
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}
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sei_cont = QTAILQ_FIRST(&s->pending_sei);
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if (sei_cont) {
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QTAILQ_REMOVE(&s->pending_sei, sei_cont, link);
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nt2_res->nt = 2;
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nt2_res->cc = sei_cont->cc;
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nt2_res->length = cpu_to_be16(sizeof(ChscSeiNt2Res));
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switch (sei_cont->cc) {
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case 1: /* error event */
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eccdf = (PciCcdfErr *)nt2_res->ccdf;
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eccdf->fid = cpu_to_be32(sei_cont->fid);
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eccdf->fh = cpu_to_be32(sei_cont->fh);
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eccdf->e = cpu_to_be32(sei_cont->e);
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eccdf->faddr = cpu_to_be64(sei_cont->faddr);
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eccdf->pec = cpu_to_be16(sei_cont->pec);
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break;
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case 2: /* availability event */
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accdf = (PciCcdfAvail *)nt2_res->ccdf;
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accdf->fid = cpu_to_be32(sei_cont->fid);
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accdf->fh = cpu_to_be32(sei_cont->fh);
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accdf->pec = cpu_to_be16(sei_cont->pec);
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break;
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default:
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abort();
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}
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g_free(sei_cont);
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rc = 0;
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}
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return rc;
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}
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int chsc_sei_nt2_have_event(void)
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{
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return 0;
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}
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return !QTAILQ_EMPTY(&s->pending_sei);
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}
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S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid)
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{
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S390PCIBusDevice *pbdev;
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int i;
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return NULL;
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}
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for (i = 0; i < PCI_SLOT_MAX; i++) {
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pbdev = &s->pbdev[i];
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if ((pbdev->fh != 0) && (pbdev->fid == fid)) {
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return pbdev;
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}
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}
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return NULL;
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}
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void s390_pci_sclp_configure(int configure, SCCB *sccb)
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{
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PciCfgSccb *psccb = (PciCfgSccb *)sccb;
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S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
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uint16_t rc;
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if (pbdev) {
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if ((configure == 1 && pbdev->configured == true) ||
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(configure == 0 && pbdev->configured == false)) {
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rc = SCLP_RC_NO_ACTION_REQUIRED;
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} else {
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pbdev->configured = !pbdev->configured;
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rc = SCLP_RC_NORMAL_COMPLETION;
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}
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} else {
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DPRINTF("sclp config %d no dev found\n", configure);
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rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
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}
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psccb->header.response_code = cpu_to_be16(rc);
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return;
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}
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static uint32_t s390_pci_get_pfid(PCIDevice *pdev)
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{
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return PCI_SLOT(pdev->devfn);
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}
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static uint32_t s390_pci_get_pfh(PCIDevice *pdev)
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{
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return PCI_SLOT(pdev->devfn) | FH_VIRT;
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}
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S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx)
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{
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S390PCIBusDevice *pbdev;
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int i;
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int j = 0;
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return NULL;
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}
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for (i = 0; i < PCI_SLOT_MAX; i++) {
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pbdev = &s->pbdev[i];
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if (pbdev->fh == 0) {
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continue;
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}
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if (j == idx) {
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return pbdev;
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}
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j++;
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}
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return NULL;
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}
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S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh)
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{
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S390PCIBusDevice *pbdev;
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int i;
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s || !fh) {
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return NULL;
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}
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for (i = 0; i < PCI_SLOT_MAX; i++) {
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pbdev = &s->pbdev[i];
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if (pbdev->fh == fh) {
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return pbdev;
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}
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}
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return NULL;
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}
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static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh,
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uint32_t fid, uint64_t faddr, uint32_t e)
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{
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SeiContainer *sei_cont;
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S390pciState *s = S390_PCI_HOST_BRIDGE(
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object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
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if (!s) {
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return;
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}
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sei_cont = g_malloc0(sizeof(SeiContainer));
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sei_cont->fh = fh;
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sei_cont->fid = fid;
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sei_cont->cc = cc;
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sei_cont->pec = pec;
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sei_cont->faddr = faddr;
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sei_cont->e = e;
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QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link);
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css_generate_css_crws(0);
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}
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static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh,
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uint32_t fid)
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{
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s390_pci_generate_event(2, pec, fh, fid, 0, 0);
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}
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static void s390_pci_generate_error_event(uint16_t pec, uint32_t fh,
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uint32_t fid, uint64_t faddr,
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uint32_t e)
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{
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s390_pci_generate_event(1, pec, fh, fid, faddr, e);
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}
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static void s390_pci_set_irq(void *opaque, int irq, int level)
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{
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/* nothing to do */
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}
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static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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/* nothing to do */
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return 0;
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}
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static uint64_t s390_pci_get_table_origin(uint64_t iota)
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{
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return iota & ~ZPCI_IOTA_RTTO_FLAG;
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}
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static unsigned int calc_rtx(dma_addr_t ptr)
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{
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return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK;
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}
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static unsigned int calc_sx(dma_addr_t ptr)
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{
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return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK;
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}
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static unsigned int calc_px(dma_addr_t ptr)
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{
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return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
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}
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static uint64_t get_rt_sto(uint64_t entry)
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{
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return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX)
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? (entry & ZPCI_RTE_ADDR_MASK)
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: 0;
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}
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static uint64_t get_st_pto(uint64_t entry)
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{
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return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX)
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? (entry & ZPCI_STE_ADDR_MASK)
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: 0;
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}
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static uint64_t s390_guest_io_table_walk(uint64_t guest_iota,
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uint64_t guest_dma_address)
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{
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uint64_t sto_a, pto_a, px_a;
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uint64_t sto, pto, pte;
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uint32_t rtx, sx, px;
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rtx = calc_rtx(guest_dma_address);
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sx = calc_sx(guest_dma_address);
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px = calc_px(guest_dma_address);
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sto_a = guest_iota + rtx * sizeof(uint64_t);
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sto = address_space_ldq(&address_space_memory, sto_a,
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MEMTXATTRS_UNSPECIFIED, NULL);
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sto = get_rt_sto(sto);
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if (!sto) {
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pte = 0;
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goto out;
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}
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pto_a = sto + sx * sizeof(uint64_t);
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pto = address_space_ldq(&address_space_memory, pto_a,
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MEMTXATTRS_UNSPECIFIED, NULL);
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pto = get_st_pto(pto);
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if (!pto) {
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pte = 0;
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goto out;
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}
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px_a = pto + px * sizeof(uint64_t);
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pte = address_space_ldq(&address_space_memory, px_a,
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MEMTXATTRS_UNSPECIFIED, NULL);
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out:
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return pte;
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}
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static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *iommu, hwaddr addr,
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bool is_write)
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{
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uint64_t pte;
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uint32_t flags;
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S390PCIBusDevice *pbdev = container_of(iommu, S390PCIBusDevice, iommu_mr);
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S390pciState *s;
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IOMMUTLBEntry ret = {
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.target_as = &address_space_memory,
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.iova = 0,
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.translated_addr = 0,
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.addr_mask = ~(hwaddr)0,
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.perm = IOMMU_NONE,
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};
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if (!pbdev->configured || !pbdev->pdev) {
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return ret;
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}
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DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr);
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s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pbdev->pdev)->qbus.parent);
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/* s390 does not have an APIC mapped to main storage so we use
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* a separate AddressSpace only for msix notifications
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*/
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if (addr == ZPCI_MSI_ADDR) {
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ret.target_as = &s->msix_notify_as;
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ret.iova = addr;
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ret.translated_addr = addr;
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ret.addr_mask = 0xfff;
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ret.perm = IOMMU_RW;
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return ret;
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}
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if (!pbdev->g_iota) {
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pbdev->error_state = true;
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pbdev->lgstg_blocked = true;
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s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
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addr, 0);
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return ret;
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}
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if (addr < pbdev->pba || addr > pbdev->pal) {
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pbdev->error_state = true;
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pbdev->lgstg_blocked = true;
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s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
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addr, 0);
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return ret;
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}
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pte = s390_guest_io_table_walk(s390_pci_get_table_origin(pbdev->g_iota),
|
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addr);
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if (!pte) {
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pbdev->error_state = true;
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pbdev->lgstg_blocked = true;
|
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s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
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addr, ERR_EVENT_Q_BIT);
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return ret;
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}
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|
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flags = pte & ZPCI_PTE_FLAG_MASK;
|
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ret.iova = addr;
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ret.translated_addr = pte & ZPCI_PTE_ADDR_MASK;
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ret.addr_mask = 0xfff;
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|
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if (flags & ZPCI_PTE_INVALID) {
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ret.perm = IOMMU_NONE;
|
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} else {
|
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ret.perm = IOMMU_RW;
|
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}
|
|
|
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return ret;
|
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}
|
|
|
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static const MemoryRegionIOMMUOps s390_iommu_ops = {
|
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.translate = s390_translate_iommu,
|
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};
|
|
|
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static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
|
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{
|
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S390pciState *s = opaque;
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|
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return &s->pbdev[PCI_SLOT(devfn)].as;
|
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}
|
|
|
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static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
|
|
{
|
|
uint8_t ind_old, ind_new;
|
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hwaddr len = 1;
|
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uint8_t *ind_addr;
|
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|
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ind_addr = cpu_physical_memory_map(ind_loc, &len, 1);
|
|
if (!ind_addr) {
|
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s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
|
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return -1;
|
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}
|
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do {
|
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ind_old = *ind_addr;
|
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ind_new = ind_old | to_be_set;
|
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} while (atomic_cmpxchg(ind_addr, ind_old, ind_new) != ind_old);
|
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cpu_physical_memory_unmap(ind_addr, len, 1, len);
|
|
|
|
return ind_old;
|
|
}
|
|
|
|
static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
|
|
unsigned int size)
|
|
{
|
|
S390PCIBusDevice *pbdev;
|
|
uint32_t io_int_word;
|
|
uint32_t fid = data >> ZPCI_MSI_VEC_BITS;
|
|
uint32_t vec = data & ZPCI_MSI_VEC_MASK;
|
|
uint64_t ind_bit;
|
|
uint32_t sum_bit;
|
|
uint32_t e = 0;
|
|
|
|
DPRINTF("write_msix data 0x%" PRIx64 " fid %d vec 0x%x\n", data, fid, vec);
|
|
|
|
pbdev = s390_pci_find_dev_by_fid(fid);
|
|
if (!pbdev) {
|
|
e |= (vec << ERR_EVENT_MVN_OFFSET);
|
|
s390_pci_generate_error_event(ERR_EVENT_NOMSI, 0, fid, addr, e);
|
|
return;
|
|
}
|
|
|
|
ind_bit = pbdev->routes.adapter.ind_offset;
|
|
sum_bit = pbdev->routes.adapter.summary_offset;
|
|
|
|
set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
|
|
0x80 >> ((ind_bit + vec) % 8));
|
|
if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
|
|
0x80 >> (sum_bit % 8))) {
|
|
io_int_word = (pbdev->isc << 27) | IO_INT_WORD_AI;
|
|
s390_io_interrupt(0, 0, 0, io_int_word);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size)
|
|
{
|
|
return 0xffffffff;
|
|
}
|
|
|
|
static const MemoryRegionOps s390_msi_ctrl_ops = {
|
|
.write = s390_msi_ctrl_write,
|
|
.read = s390_msi_ctrl_read,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
void s390_pcihost_iommu_configure(S390PCIBusDevice *pbdev, bool enable)
|
|
{
|
|
pbdev->configured = false;
|
|
|
|
if (enable) {
|
|
uint64_t size = pbdev->pal - pbdev->pba + 1;
|
|
memory_region_init_iommu(&pbdev->iommu_mr, OBJECT(&pbdev->mr),
|
|
&s390_iommu_ops, "iommu-s390", size);
|
|
memory_region_add_subregion(&pbdev->mr, pbdev->pba, &pbdev->iommu_mr);
|
|
} else {
|
|
memory_region_del_subregion(&pbdev->mr, &pbdev->iommu_mr);
|
|
}
|
|
|
|
pbdev->configured = true;
|
|
}
|
|
|
|
static void s390_pcihost_init_as(S390pciState *s)
|
|
{
|
|
int i;
|
|
S390PCIBusDevice *pbdev;
|
|
|
|
for (i = 0; i < PCI_SLOT_MAX; i++) {
|
|
pbdev = &s->pbdev[i];
|
|
memory_region_init(&pbdev->mr, OBJECT(s),
|
|
"iommu-root-s390", UINT64_MAX);
|
|
address_space_init(&pbdev->as, &pbdev->mr, "iommu-pci");
|
|
}
|
|
|
|
memory_region_init_io(&s->msix_notify_mr, OBJECT(s),
|
|
&s390_msi_ctrl_ops, s, "msix-s390", UINT64_MAX);
|
|
address_space_init(&s->msix_notify_as, &s->msix_notify_mr, "msix-pci");
|
|
}
|
|
|
|
static int s390_pcihost_init(SysBusDevice *dev)
|
|
{
|
|
PCIBus *b;
|
|
BusState *bus;
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
|
|
S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
|
|
|
|
DPRINTF("host_init\n");
|
|
|
|
b = pci_register_bus(DEVICE(dev), NULL,
|
|
s390_pci_set_irq, s390_pci_map_irq, NULL,
|
|
get_system_memory(), get_system_io(), 0, 64,
|
|
TYPE_PCI_BUS);
|
|
s390_pcihost_init_as(s);
|
|
pci_setup_iommu(b, s390_pci_dma_iommu, s);
|
|
|
|
bus = BUS(b);
|
|
qbus_set_hotplug_handler(bus, DEVICE(dev), NULL);
|
|
phb->bus = b;
|
|
QTAILQ_INIT(&s->pending_sei);
|
|
return 0;
|
|
}
|
|
|
|
static int s390_pcihost_setup_msix(S390PCIBusDevice *pbdev)
|
|
{
|
|
uint8_t pos;
|
|
uint16_t ctrl;
|
|
uint32_t table, pba;
|
|
|
|
pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX);
|
|
if (!pos) {
|
|
pbdev->msix.available = false;
|
|
return 0;
|
|
}
|
|
|
|
ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_CAP_FLAGS,
|
|
pci_config_size(pbdev->pdev), sizeof(ctrl));
|
|
table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE,
|
|
pci_config_size(pbdev->pdev), sizeof(table));
|
|
pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA,
|
|
pci_config_size(pbdev->pdev), sizeof(pba));
|
|
|
|
pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
|
|
pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
|
|
pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
|
|
pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
|
|
pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
|
|
pbdev->msix.available = true;
|
|
return 0;
|
|
}
|
|
|
|
static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev,
|
|
DeviceState *dev, Error **errp)
|
|
{
|
|
PCIDevice *pci_dev = PCI_DEVICE(dev);
|
|
S390PCIBusDevice *pbdev;
|
|
S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
|
|
->qbus.parent);
|
|
|
|
pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
|
|
|
|
pbdev->fid = s390_pci_get_pfid(pci_dev);
|
|
pbdev->pdev = pci_dev;
|
|
pbdev->configured = true;
|
|
pbdev->fh = s390_pci_get_pfh(pci_dev);
|
|
|
|
s390_pcihost_setup_msix(pbdev);
|
|
|
|
if (dev->hotplugged) {
|
|
s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY,
|
|
pbdev->fh, pbdev->fid);
|
|
s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED,
|
|
pbdev->fh, pbdev->fid);
|
|
}
|
|
return;
|
|
}
|
|
|
|
static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev,
|
|
DeviceState *dev, Error **errp)
|
|
{
|
|
PCIDevice *pci_dev = PCI_DEVICE(dev);
|
|
S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
|
|
->qbus.parent);
|
|
S390PCIBusDevice *pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
|
|
|
|
if (pbdev->configured) {
|
|
pbdev->configured = false;
|
|
s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES,
|
|
pbdev->fh, pbdev->fid);
|
|
}
|
|
|
|
s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED,
|
|
pbdev->fh, pbdev->fid);
|
|
pbdev->fh = 0;
|
|
pbdev->fid = 0;
|
|
pbdev->pdev = NULL;
|
|
object_unparent(OBJECT(pci_dev));
|
|
}
|
|
|
|
static void s390_pcihost_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
|
|
|
|
dc->cannot_instantiate_with_device_add_yet = true;
|
|
k->init = s390_pcihost_init;
|
|
hc->plug = s390_pcihost_hot_plug;
|
|
hc->unplug = s390_pcihost_hot_unplug;
|
|
msi_supported = true;
|
|
}
|
|
|
|
static const TypeInfo s390_pcihost_info = {
|
|
.name = TYPE_S390_PCI_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(S390pciState),
|
|
.class_init = s390_pcihost_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_HOTPLUG_HANDLER },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void s390_pci_register_types(void)
|
|
{
|
|
type_register_static(&s390_pcihost_info);
|
|
}
|
|
|
|
type_init(s390_pci_register_types)
|