qemu-patch-raspberry4/target/riscv
Michael Clark eab1586257
RISC-V: Convert cpu definition to future model
- Model borrowed from target/sh4/cpu.c
- Rewrote riscv_cpu_list to use object_class_get_list
- Dropped 'struct RISCVCPUInfo' and used TypeInfo array
- Replaced riscv_cpu_register_types with DEFINE_TYPES
- Marked base class as abstract
- Fixes -cpu list

Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2018-03-28 11:12:02 -07:00
..
cpu.c RISC-V: Convert cpu definition to future model 2018-03-28 11:12:02 -07:00
cpu.h cpu: add CPU_RESOLVING_TYPE macro 2018-03-19 14:10:36 -03:00
cpu_bits.h
cpu_user.h RISC-V Linux User Emulation 2018-03-07 08:30:28 +13:00
fpu_helper.c RISC-V FPU Support 2018-03-07 08:30:28 +13:00
gdbstub.c RISC-V GDB Stub 2018-03-07 08:30:28 +13:00
helper.c RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
helper.h RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
Makefile.objs RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
op_helper.c RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
pmp.c RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
pmp.h RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
translate.c RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00