git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@296 c046a42c-6fe2-441c-8c8c-71466251a162
636 lines
18 KiB
C
636 lines
18 KiB
C
/*
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* i386 emulator main execution loop
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "config.h"
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#ifdef TARGET_I386
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#include "exec-i386.h"
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#endif
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#ifdef TARGET_ARM
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#include "exec-arm.h"
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#endif
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#include "disas.h"
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//#define DEBUG_EXEC
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//#define DEBUG_SIGNAL
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#if defined(TARGET_ARM)
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/* XXX: unify with i386 target */
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void cpu_loop_exit(void)
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{
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longjmp(env->jmp_env, 1);
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}
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#endif
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/* main execution loop */
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int cpu_exec(CPUState *env1)
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{
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int saved_T0, saved_T1, saved_T2;
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CPUState *saved_env;
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#ifdef reg_EAX
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int saved_EAX;
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#endif
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#ifdef reg_ECX
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int saved_ECX;
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#endif
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#ifdef reg_EDX
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int saved_EDX;
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#endif
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#ifdef reg_EBX
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int saved_EBX;
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#endif
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#ifdef reg_ESP
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int saved_ESP;
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#endif
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#ifdef reg_EBP
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int saved_EBP;
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#endif
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#ifdef reg_ESI
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int saved_ESI;
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#endif
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#ifdef reg_EDI
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int saved_EDI;
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#endif
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#ifdef __sparc__
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int saved_i7, tmp_T0;
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#endif
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int code_gen_size, ret, interrupt_request;
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void (*gen_func)(void);
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TranslationBlock *tb, **ptb;
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uint8_t *tc_ptr, *cs_base, *pc;
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unsigned int flags;
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/* first we save global registers */
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saved_T0 = T0;
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saved_T1 = T1;
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saved_T2 = T2;
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saved_env = env;
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env = env1;
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#ifdef __sparc__
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/* we also save i7 because longjmp may not restore it */
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asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
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#endif
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#if defined(TARGET_I386)
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#ifdef reg_EAX
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saved_EAX = EAX;
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EAX = env->regs[R_EAX];
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#endif
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#ifdef reg_ECX
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saved_ECX = ECX;
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ECX = env->regs[R_ECX];
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#endif
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#ifdef reg_EDX
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saved_EDX = EDX;
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EDX = env->regs[R_EDX];
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#endif
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#ifdef reg_EBX
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saved_EBX = EBX;
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EBX = env->regs[R_EBX];
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#endif
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#ifdef reg_ESP
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saved_ESP = ESP;
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ESP = env->regs[R_ESP];
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#endif
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#ifdef reg_EBP
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saved_EBP = EBP;
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EBP = env->regs[R_EBP];
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#endif
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#ifdef reg_ESI
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saved_ESI = ESI;
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ESI = env->regs[R_ESI];
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#endif
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#ifdef reg_EDI
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saved_EDI = EDI;
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EDI = env->regs[R_EDI];
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#endif
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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DF = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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#elif defined(TARGET_ARM)
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{
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unsigned int psr;
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psr = env->cpsr;
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env->CF = (psr >> 29) & 1;
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env->NZF = (psr & 0xc0000000) ^ 0x40000000;
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env->VF = (psr << 3) & 0x80000000;
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env->cpsr = psr & ~0xf0000000;
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}
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#else
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#error unsupported target CPU
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#endif
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env->exception_index = -1;
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/* prepare setjmp context for exception handling */
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for(;;) {
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if (setjmp(env->jmp_env) == 0) {
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/* if an exception is pending, we execute it here */
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if (env->exception_index >= 0) {
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if (env->exception_index >= EXCP_INTERRUPT) {
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/* exit request from the cpu execution loop */
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ret = env->exception_index;
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break;
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} else if (env->user_mode_only) {
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/* if user mode only, we simulate a fake exception
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which will be hanlded outside the cpu execution
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loop */
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#if defined(TARGET_I386)
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do_interrupt_user(env->exception_index,
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env->exception_is_int,
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env->error_code,
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env->exception_next_eip);
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#endif
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ret = env->exception_index;
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break;
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} else {
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#if defined(TARGET_I386)
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/* simulate a real cpu exception. On i386, it can
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trigger new exceptions, but we do not handle
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double or triple faults yet. */
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do_interrupt(env->exception_index,
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env->exception_is_int,
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env->error_code,
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env->exception_next_eip);
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#endif
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}
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env->exception_index = -1;
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}
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T0 = 0; /* force lookup of first TB */
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for(;;) {
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#ifdef __sparc__
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/* g1 can be modified by some libc? functions */
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tmp_T0 = T0;
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#endif
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interrupt_request = env->interrupt_request;
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if (interrupt_request) {
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#if defined(TARGET_I386)
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/* if hardware interrupt pending, we execute it */
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->eflags & IF_MASK)) {
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int intno;
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intno = cpu_x86_get_pic_interrupt(env);
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if (loglevel) {
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fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
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}
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do_interrupt(intno, 0, 0, 0);
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env->interrupt_request &= ~CPU_INTERRUPT_HARD;
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}
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#endif
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if (interrupt_request & CPU_INTERRUPT_EXIT) {
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env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
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env->exception_index = EXCP_INTERRUPT;
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cpu_loop_exit();
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}
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}
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#ifdef DEBUG_EXEC
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if (loglevel) {
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#if defined(TARGET_I386)
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/* restore flags in standard format */
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env->regs[R_EAX] = EAX;
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env->regs[R_EBX] = EBX;
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env->regs[R_ECX] = ECX;
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env->regs[R_EDX] = EDX;
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env->regs[R_ESI] = ESI;
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env->regs[R_EDI] = EDI;
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env->regs[R_EBP] = EBP;
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env->regs[R_ESP] = ESP;
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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#elif defined(TARGET_ARM)
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cpu_arm_dump_state(env, logfile, 0);
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#else
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#error unsupported target CPU
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#endif
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}
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#endif
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/* we compute the CPU state. We assume it will not
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change during the whole generated block. */
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#if defined(TARGET_I386)
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flags = (env->segs[R_CS].flags & DESC_B_MASK)
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>> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT);
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flags |= (env->segs[R_SS].flags & DESC_B_MASK)
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>> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT);
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flags |= (((unsigned long)env->segs[R_DS].base |
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(unsigned long)env->segs[R_ES].base |
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(unsigned long)env->segs[R_SS].base) != 0) <<
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GEN_FLAG_ADDSEG_SHIFT;
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if (!(env->eflags & VM_MASK)) {
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flags |= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT;
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} else {
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/* NOTE: a dummy CPL is kept */
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flags |= (1 << GEN_FLAG_VM_SHIFT);
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flags |= (3 << GEN_FLAG_CPL_SHIFT);
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}
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flags |= (env->eflags & (IOPL_MASK | TF_MASK));
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cs_base = env->segs[R_CS].base;
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pc = cs_base + env->eip;
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#elif defined(TARGET_ARM)
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flags = 0;
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cs_base = 0;
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pc = (uint8_t *)env->regs[15];
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#else
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#error unsupported CPU
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#endif
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
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flags);
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if (!tb) {
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spin_lock(&tb_lock);
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/* if no translated code available, then translate it now */
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tb = tb_alloc((unsigned long)pc);
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if (!tb) {
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/* flush must be done */
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tb_flush();
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/* cannot fail at this point */
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tb = tb_alloc((unsigned long)pc);
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/* don't forget to invalidate previous TB info */
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ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
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T0 = 0;
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}
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tc_ptr = code_gen_ptr;
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tb->tc_ptr = tc_ptr;
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tb->cs_base = (unsigned long)cs_base;
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tb->flags = flags;
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ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
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#if defined(TARGET_I386)
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/* XXX: suppress that, this is incorrect */
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/* if invalid instruction, signal it */
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if (ret != 0) {
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/* NOTE: the tb is allocated but not linked, so we
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can leave it */
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spin_unlock(&tb_lock);
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raise_exception(EXCP06_ILLOP);
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}
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#endif
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*ptb = tb;
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tb->hash_next = NULL;
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tb_link(tb);
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
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spin_unlock(&tb_lock);
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}
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#ifdef DEBUG_EXEC
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if (loglevel) {
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fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
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(long)tb->tc_ptr, (long)tb->pc,
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lookup_symbol((void *)tb->pc));
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}
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#endif
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#ifdef __sparc__
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T0 = tmp_T0;
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#endif
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/* see if we can patch the calling TB. XXX: remove TF test */
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if (T0 != 0
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#if defined(TARGET_I386)
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&& !(env->eflags & TF_MASK)
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#endif
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) {
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spin_lock(&tb_lock);
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tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
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spin_unlock(&tb_lock);
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}
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tc_ptr = tb->tc_ptr;
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env->current_tb = tb;
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/* execute the generated code */
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gen_func = (void *)tc_ptr;
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#if defined(__sparc__)
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__asm__ __volatile__("call %0\n\t"
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"mov %%o7,%%i0"
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: /* no outputs */
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: "r" (gen_func)
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: "i0", "i1", "i2", "i3", "i4", "i5");
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#elif defined(__arm__)
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asm volatile ("mov pc, %0\n\t"
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".global exec_loop\n\t"
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"exec_loop:\n\t"
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: /* no outputs */
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: "r" (gen_func)
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: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
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#else
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gen_func();
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#endif
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env->current_tb = NULL;
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}
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} else {
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}
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} /* for(;;) */
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#if defined(TARGET_I386)
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/* restore flags in standard format */
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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/* restore global registers */
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#ifdef reg_EAX
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EAX = saved_EAX;
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#endif
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#ifdef reg_ECX
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ECX = saved_ECX;
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#endif
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#ifdef reg_EDX
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EDX = saved_EDX;
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#endif
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#ifdef reg_EBX
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EBX = saved_EBX;
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#endif
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#ifdef reg_ESP
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ESP = saved_ESP;
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#endif
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#ifdef reg_EBP
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EBP = saved_EBP;
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#endif
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#ifdef reg_ESI
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ESI = saved_ESI;
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#endif
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#ifdef reg_EDI
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EDI = saved_EDI;
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#endif
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#elif defined(TARGET_ARM)
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{
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int ZF;
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ZF = (env->NZF == 0);
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env->cpsr = env->cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
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(env->CF << 29) | ((env->VF & 0x80000000) >> 3);
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}
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#else
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#error unsupported target CPU
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#endif
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#ifdef __sparc__
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asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
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#endif
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T0 = saved_T0;
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T1 = saved_T1;
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T2 = saved_T2;
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env = saved_env;
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return ret;
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}
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#if defined(TARGET_I386)
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void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
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{
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CPUX86State *saved_env;
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saved_env = env;
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env = s;
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if (env->eflags & VM_MASK) {
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SegmentCache *sc;
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selector &= 0xffff;
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sc = &env->segs[seg_reg];
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/* NOTE: in VM86 mode, limit and flags are never reloaded,
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so we must load them here */
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sc->base = (void *)(selector << 4);
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sc->limit = 0xffff;
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sc->flags = 0;
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sc->selector = selector;
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} else {
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load_seg(seg_reg, selector, 0);
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}
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env = saved_env;
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}
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void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
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{
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CPUX86State *saved_env;
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saved_env = env;
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env = s;
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helper_fsave(ptr, data32);
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env = saved_env;
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}
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void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
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{
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CPUX86State *saved_env;
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saved_env = env;
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env = s;
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helper_frstor(ptr, data32);
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env = saved_env;
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}
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#endif /* TARGET_I386 */
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#include <signal.h>
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#include <sys/ucontext.h>
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#if defined(TARGET_I386)
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/* 'pc' is the host PC at which the exception was raised. 'address' is
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the effective address of the memory exception. 'is_write' is 1 if a
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write caused the exception and otherwise 0'. 'old_set' is the
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signal set which should be restored */
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static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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int is_write, sigset_t *old_set)
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{
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TranslationBlock *tb;
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int ret;
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if (cpu_single_env)
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env = cpu_single_env; /* XXX: find a correct solution for multithread */
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#if defined(DEBUG_SIGNAL)
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
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pc, address, is_write, *(unsigned long *)old_set);
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#endif
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/* XXX: locking issue */
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if (is_write && page_unprotect(address)) {
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return 1;
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}
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/* see if it is an MMU fault */
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ret = cpu_x86_handle_mmu_fault(env, address, is_write);
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if (ret < 0)
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return 0; /* not an MMU fault */
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if (ret == 0)
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return 1; /* the MMU fault was handled without causing real CPU fault */
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/* now we have a real cpu fault */
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tb = tb_find_pc(pc);
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc);
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}
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#if 0
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printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
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env->eip, env->cr[2], env->error_code);
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#endif
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/* we restore the process signal mask as the sigreturn should
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do it (XXX: use sigsetjmp) */
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sigprocmask(SIG_SETMASK, old_set, NULL);
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raise_exception_err(EXCP0E_PAGE, env->error_code);
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/* never comes here */
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return 1;
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}
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#elif defined(TARGET_ARM)
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static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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int is_write, sigset_t *old_set)
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{
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/* XXX: do more */
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return 0;
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}
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#else
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#error unsupported target CPU
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#endif
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#if defined(__i386__)
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int cpu_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
|
|
#ifndef REG_EIP
|
|
/* for glibc 2.1 */
|
|
#define REG_EIP EIP
|
|
#define REG_ERR ERR
|
|
#define REG_TRAPNO TRAPNO
|
|
#endif
|
|
pc = uc->uc_mcontext.gregs[REG_EIP];
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
|
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
|
|
&uc->uc_sigmask);
|
|
}
|
|
|
|
#elif defined(__powerpc)
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
struct pt_regs *regs = uc->uc_mcontext.regs;
|
|
unsigned long pc;
|
|
int is_write;
|
|
|
|
pc = regs->nip;
|
|
is_write = 0;
|
|
#if 0
|
|
/* ppc 4xx case */
|
|
if (regs->dsisr & 0x00800000)
|
|
is_write = 1;
|
|
#else
|
|
if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
|
|
is_write = 1;
|
|
#endif
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, &uc->uc_sigmask);
|
|
}
|
|
|
|
#elif defined(__alpha__)
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
uint32_t *pc = uc->uc_mcontext.sc_pc;
|
|
uint32_t insn = *pc;
|
|
int is_write = 0;
|
|
|
|
/* XXX: need kernel patch to get write flag faster */
|
|
switch (insn >> 26) {
|
|
case 0x0d: // stw
|
|
case 0x0e: // stb
|
|
case 0x0f: // stq_u
|
|
case 0x24: // stf
|
|
case 0x25: // stg
|
|
case 0x26: // sts
|
|
case 0x27: // stt
|
|
case 0x2c: // stl
|
|
case 0x2d: // stq
|
|
case 0x2e: // stl_c
|
|
case 0x2f: // stq_c
|
|
is_write = 1;
|
|
}
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, &uc->uc_sigmask);
|
|
}
|
|
#elif defined(__sparc__)
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
uint32_t *regs = (uint32_t *)(info + 1);
|
|
void *sigmask = (regs + 20);
|
|
unsigned long pc;
|
|
int is_write;
|
|
uint32_t insn;
|
|
|
|
/* XXX: is there a standard glibc define ? */
|
|
pc = regs[1];
|
|
/* XXX: need kernel patch to get write flag faster */
|
|
is_write = 0;
|
|
insn = *(uint32_t *)pc;
|
|
if ((insn >> 30) == 3) {
|
|
switch((insn >> 19) & 0x3f) {
|
|
case 0x05: // stb
|
|
case 0x06: // sth
|
|
case 0x04: // st
|
|
case 0x07: // std
|
|
case 0x24: // stf
|
|
case 0x27: // stdf
|
|
case 0x25: // stfsr
|
|
is_write = 1;
|
|
break;
|
|
}
|
|
}
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, sigmask);
|
|
}
|
|
|
|
#elif defined(__arm__)
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
int is_write;
|
|
|
|
pc = uc->uc_mcontext.gregs[R15];
|
|
/* XXX: compute is_write */
|
|
is_write = 0;
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write,
|
|
&uc->uc_sigmask);
|
|
}
|
|
|
|
#else
|
|
|
|
#error host CPU specific signal handler needed
|
|
|
|
#endif
|