PnvChip is defined twice and this can confuse old compilers : CC ppc64-softmmu/hw/ppc/pnv_xscom.o In file included from qemu.git/hw/ppc/pnv.c:29: qemu.git/include/hw/ppc/pnv.h:60: error: redefinition of typedef ‘PnvChip’ qemu.git/include/hw/ppc/pnv_xscom.h:24: note: previous declaration of ‘PnvChip’ was here make[1]: *** [hw/ppc/pnv.o] Error 1 make[1]: *** Waiting for unfinished jobs.... Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
473 lines
15 KiB
C
473 lines
15 KiB
C
/*
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* QEMU PowerPC PowerNV LPC controller
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "sysemu/sysemu.h"
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#include "target-ppc/cpu.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_lpc.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/ppc/fdt.h"
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#include <libfdt.h>
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enum {
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ECCB_CTL = 0,
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ECCB_RESET = 1,
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ECCB_STAT = 2,
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ECCB_DATA = 3,
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};
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/* OPB Master LS registers */
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#define OPB_MASTER_LS_IRQ_STAT 0x50
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#define OPB_MASTER_IRQ_LPC 0x00000800
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#define OPB_MASTER_LS_IRQ_MASK 0x54
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#define OPB_MASTER_LS_IRQ_POL 0x58
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#define OPB_MASTER_LS_IRQ_INPUT 0x5c
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/* LPC HC registers */
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#define LPC_HC_FW_SEG_IDSEL 0x24
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#define LPC_HC_FW_RD_ACC_SIZE 0x28
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#define LPC_HC_FW_RD_1B 0x00000000
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#define LPC_HC_FW_RD_2B 0x01000000
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#define LPC_HC_FW_RD_4B 0x02000000
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#define LPC_HC_FW_RD_16B 0x04000000
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#define LPC_HC_FW_RD_128B 0x07000000
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#define LPC_HC_IRQSER_CTRL 0x30
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#define LPC_HC_IRQSER_EN 0x80000000
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#define LPC_HC_IRQSER_QMODE 0x40000000
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#define LPC_HC_IRQSER_START_MASK 0x03000000
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#define LPC_HC_IRQSER_START_4CLK 0x00000000
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#define LPC_HC_IRQSER_START_6CLK 0x01000000
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#define LPC_HC_IRQSER_START_8CLK 0x02000000
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#define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */
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#define LPC_HC_IRQSTAT 0x38
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#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
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#define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
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#define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000
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#define LPC_HC_IRQ_LRESET 0x00000400
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#define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080
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#define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040
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#define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020
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#define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010
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#define LPC_HC_IRQ_SYNC_TARG_TAR_ERR 0x00000008
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#define LPC_HC_IRQ_SYNC_BM_TAR_ERR 0x00000004
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#define LPC_HC_IRQ_SYNC_BM0_REQ 0x00000002
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#define LPC_HC_IRQ_SYNC_BM1_REQ 0x00000001
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#define LPC_HC_ERROR_ADDRESS 0x40
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#define LPC_OPB_SIZE 0x100000000ull
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#define ISA_IO_SIZE 0x00010000
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#define ISA_MEM_SIZE 0x10000000
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#define LPC_IO_OPB_ADDR 0xd0010000
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#define LPC_IO_OPB_SIZE 0x00010000
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#define LPC_MEM_OPB_ADDR 0xe0010000
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#define LPC_MEM_OPB_SIZE 0x10000000
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#define LPC_FW_OPB_ADDR 0xf0000000
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#define LPC_FW_OPB_SIZE 0x10000000
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#define LPC_OPB_REGS_OPB_ADDR 0xc0010000
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#define LPC_OPB_REGS_OPB_SIZE 0x00002000
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#define LPC_HC_REGS_OPB_ADDR 0xc0012000
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#define LPC_HC_REGS_OPB_SIZE 0x00001000
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/*
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* TODO: the "primary" cell should only be added on chip 0. This is
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* how skiboot chooses the default LPC controller on multichip
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* systems.
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*
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* It would be easly done if we can change the populate() interface to
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* replace the PnvXScomInterface parameter by a PnvChip one
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*/
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static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
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{
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const char compat[] = "ibm,power8-lpc\0ibm,lpc";
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char *name;
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int offset;
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uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE;
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uint32_t reg[] = {
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cpu_to_be32(lpc_pcba),
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cpu_to_be32(PNV_XSCOM_LPC_SIZE)
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};
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name = g_strdup_printf("isa@%x", lpc_pcba);
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offset = fdt_add_subnode(fdt, xscom_offset, name);
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_FDT(offset);
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g_free(name);
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_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
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_FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
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_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
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_FDT((fdt_setprop(fdt, offset, "primary", NULL, 0)));
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_FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
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return 0;
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}
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/*
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* These read/write handlers of the OPB address space should be common
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* with the P9 LPC Controller which uses direct MMIOs.
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*
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* TODO: rework to use address_space_stq() and address_space_ldq()
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* instead.
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*/
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static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
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int sz)
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{
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bool success;
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/* XXX Handle access size limits and FW read caching here */
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success = !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
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data, sz, false);
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return success;
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}
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static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
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int sz)
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{
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bool success;
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/* XXX Handle access size limits here */
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success = !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
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data, sz, true);
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return success;
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}
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#define ECCB_CTL_READ (1ull << (63 - 15))
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#define ECCB_CTL_SZ_LSH (63 - 7)
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#define ECCB_CTL_SZ_MASK (0xfull << ECCB_CTL_SZ_LSH)
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#define ECCB_CTL_ADDR_MASK 0xffffffffu;
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#define ECCB_STAT_OP_DONE (1ull << (63 - 52))
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#define ECCB_STAT_OP_ERR (1ull << (63 - 52))
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#define ECCB_STAT_RD_DATA_LSH (63 - 37)
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#define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH)
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static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd)
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{
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/* XXX Check for magic bits at the top, addr size etc... */
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unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH;
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uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK;
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uint8_t data[4];
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bool success;
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if (cmd & ECCB_CTL_READ) {
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success = opb_read(lpc, opb_addr, data, sz);
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if (success) {
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lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
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(((uint64_t)data[0]) << 24 |
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((uint64_t)data[1]) << 16 |
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((uint64_t)data[2]) << 8 |
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((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH;
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} else {
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lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
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(0xffffffffull << ECCB_STAT_RD_DATA_LSH);
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}
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} else {
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data[0] = lpc->eccb_data_reg >> 24;
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data[1] = lpc->eccb_data_reg >> 16;
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data[2] = lpc->eccb_data_reg >> 8;
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data[3] = lpc->eccb_data_reg;
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success = opb_write(lpc, opb_addr, data, sz);
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lpc->eccb_stat_reg = ECCB_STAT_OP_DONE;
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}
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/* XXX Which error bit (if any) to signal OPB error ? */
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}
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static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size)
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{
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PnvLpcController *lpc = PNV_LPC(opaque);
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uint32_t offset = addr >> 3;
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uint64_t val = 0;
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switch (offset & 3) {
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case ECCB_CTL:
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case ECCB_RESET:
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val = 0;
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break;
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case ECCB_STAT:
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val = lpc->eccb_stat_reg;
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lpc->eccb_stat_reg = 0;
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break;
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case ECCB_DATA:
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val = ((uint64_t)lpc->eccb_data_reg) << 32;
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break;
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}
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return val;
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}
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static void pnv_lpc_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvLpcController *lpc = PNV_LPC(opaque);
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uint32_t offset = addr >> 3;
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switch (offset & 3) {
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case ECCB_CTL:
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pnv_lpc_do_eccb(lpc, val);
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break;
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case ECCB_RESET:
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/* XXXX */
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break;
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case ECCB_STAT:
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break;
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case ECCB_DATA:
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lpc->eccb_data_reg = val >> 32;
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break;
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}
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}
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static const MemoryRegionOps pnv_lpc_xscom_ops = {
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.read = pnv_lpc_xscom_read,
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.write = pnv_lpc_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
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{
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PnvLpcController *lpc = opaque;
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uint64_t val = 0xfffffffffffffffful;
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switch (addr) {
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case LPC_HC_FW_SEG_IDSEL:
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val = lpc->lpc_hc_fw_seg_idsel;
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break;
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case LPC_HC_FW_RD_ACC_SIZE:
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val = lpc->lpc_hc_fw_rd_acc_size;
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break;
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case LPC_HC_IRQSER_CTRL:
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val = lpc->lpc_hc_irqser_ctrl;
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break;
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case LPC_HC_IRQMASK:
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val = lpc->lpc_hc_irqmask;
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break;
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case LPC_HC_IRQSTAT:
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val = lpc->lpc_hc_irqstat;
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break;
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case LPC_HC_ERROR_ADDRESS:
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val = lpc->lpc_hc_error_addr;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr);
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}
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return val;
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}
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static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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PnvLpcController *lpc = opaque;
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/* XXX Filter out reserved bits */
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switch (addr) {
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case LPC_HC_FW_SEG_IDSEL:
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/* XXX Actually figure out how that works as this impact
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* memory regions/aliases
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*/
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lpc->lpc_hc_fw_seg_idsel = val;
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break;
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case LPC_HC_FW_RD_ACC_SIZE:
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lpc->lpc_hc_fw_rd_acc_size = val;
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break;
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case LPC_HC_IRQSER_CTRL:
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lpc->lpc_hc_irqser_ctrl = val;
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break;
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case LPC_HC_IRQMASK:
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lpc->lpc_hc_irqmask = val;
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break;
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case LPC_HC_IRQSTAT:
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lpc->lpc_hc_irqstat &= ~val;
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break;
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case LPC_HC_ERROR_ADDRESS:
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr);
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}
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}
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static const MemoryRegionOps lpc_hc_ops = {
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.read = lpc_hc_read,
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.write = lpc_hc_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
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{
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PnvLpcController *lpc = opaque;
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uint64_t val = 0xfffffffffffffffful;
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switch (addr) {
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case OPB_MASTER_LS_IRQ_STAT:
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val = lpc->opb_irq_stat;
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break;
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case OPB_MASTER_LS_IRQ_MASK:
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val = lpc->opb_irq_mask;
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break;
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case OPB_MASTER_LS_IRQ_POL:
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val = lpc->opb_irq_pol;
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break;
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case OPB_MASTER_LS_IRQ_INPUT:
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val = lpc->opb_irq_input;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr);
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}
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return val;
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}
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static void opb_master_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvLpcController *lpc = opaque;
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switch (addr) {
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case OPB_MASTER_LS_IRQ_STAT:
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lpc->opb_irq_stat &= ~val;
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break;
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case OPB_MASTER_LS_IRQ_MASK:
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/* XXX Filter out reserved bits */
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lpc->opb_irq_mask = val;
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break;
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case OPB_MASTER_LS_IRQ_POL:
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/* XXX Filter out reserved bits */
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lpc->opb_irq_pol = val;
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break;
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case OPB_MASTER_LS_IRQ_INPUT:
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/* Read only */
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr);
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}
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}
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static const MemoryRegionOps opb_master_ops = {
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.read = opb_master_read,
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.write = opb_master_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void pnv_lpc_realize(DeviceState *dev, Error **errp)
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{
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PnvLpcController *lpc = PNV_LPC(dev);
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/* Reg inits */
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lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
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/* Create address space and backing MR for the OPB bus */
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memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull);
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address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb");
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/* Create ISA IO and Mem space regions which are the root of
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* the ISA bus (ie, ISA address spaces). We don't create a
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* separate one for FW which we alias to memory.
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*/
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memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE);
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memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE);
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/* Create windows from the OPB space to the ISA space */
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memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io",
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&lpc->isa_io, 0, LPC_IO_OPB_SIZE);
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memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR,
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&lpc->opb_isa_io);
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memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem",
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&lpc->isa_mem, 0, LPC_MEM_OPB_SIZE);
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memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR,
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&lpc->opb_isa_mem);
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memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw",
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&lpc->isa_mem, 0, LPC_FW_OPB_SIZE);
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memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR,
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&lpc->opb_isa_fw);
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/* Create MMIO regions for LPC HC and OPB registers */
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memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops,
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lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE);
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memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR,
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&lpc->opb_master_regs);
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memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc,
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"lpc-hc", LPC_HC_REGS_OPB_SIZE);
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memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
|
|
&lpc->lpc_hc_regs);
|
|
|
|
/* XScom region for LPC registers */
|
|
pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev),
|
|
&pnv_lpc_xscom_ops, lpc, "xscom-lpc",
|
|
PNV_XSCOM_LPC_SIZE);
|
|
}
|
|
|
|
static void pnv_lpc_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
|
|
|
|
xdc->populate = pnv_lpc_populate;
|
|
|
|
dc->realize = pnv_lpc_realize;
|
|
}
|
|
|
|
static const TypeInfo pnv_lpc_info = {
|
|
.name = TYPE_PNV_LPC,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(PnvLpcController),
|
|
.class_init = pnv_lpc_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_PNV_XSCOM_INTERFACE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void pnv_lpc_register_types(void)
|
|
{
|
|
type_register_static(&pnv_lpc_info);
|
|
}
|
|
|
|
type_init(pnv_lpc_register_types)
|