The 'intc' pointer of the CPU references the interrupt presenter in the XICS interrupt mode. When the XIVE interrupt mode is available and activated, the machine will need to reassign this pointer to reflect the change. Moving this assignment under the realize routine of the CPU will ease the process when the interrupt mode is toggled. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
242 lines
6.9 KiB
C
242 lines
6.9 KiB
C
/*
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* QEMU PowerPC PowerNV CPU Core model
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public License
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* as published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "sysemu/sysemu.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/ppc.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_core.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/ppc/xics.h"
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static const char *pnv_core_cpu_typename(PnvCore *pc)
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{
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const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
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int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
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char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
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const char *cpu_type = object_class_get_name(object_class_by_name(s));
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g_free(s);
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return cpu_type;
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}
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static void powernv_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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cpu_reset(cs);
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/*
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* the skiboot firmware elects a primary thread to initialize the
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* system and it can be any.
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*/
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env->gpr[3] = PNV_FDT_ADDR;
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env->nip = 0x10;
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env->msr |= MSR_HVB; /* Hypervisor mode */
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}
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static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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int core_pir;
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int thread_index = 0; /* TODO: TCG supports only one thread */
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ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
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core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
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/*
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* The PIR of a thread is the core PIR + the thread index. We will
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* need to find a way to get the thread index when TCG supports
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* more than 1. We could use the object name ?
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*/
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pir->default_value = core_pir + thread_index;
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
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qemu_register_reset(powernv_cpu_reset, cpu);
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}
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/*
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* These values are read by the PowerNV HW monitors under Linux
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*/
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#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
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#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
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static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
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unsigned int width)
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{
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uint32_t offset = addr >> 3;
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uint64_t val = 0;
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/* The result should be 38 C */
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switch (offset) {
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case PNV_XSCOM_EX_DTS_RESULT0:
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val = 0x26f024f023f0000ull;
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break;
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case PNV_XSCOM_EX_DTS_RESULT1:
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val = 0x24f000000000000ull;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx,
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addr);
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}
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return val;
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}
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static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int width)
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{
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qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx,
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addr);
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}
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static const MemoryRegionOps pnv_core_xscom_ops = {
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.read = pnv_core_xscom_read,
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.write = pnv_core_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp)
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{
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Error *local_err = NULL;
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CPUState *cs = CPU(child);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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object_property_set_bool(child, true, "realized", &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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cpu->intc = icp_create(child, TYPE_PNV_ICP, xi, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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powernv_cpu_init(cpu, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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static void pnv_core_realize(DeviceState *dev, Error **errp)
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{
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PnvCore *pc = PNV_CORE(OBJECT(dev));
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CPUCore *cc = CPU_CORE(OBJECT(dev));
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const char *typename = pnv_core_cpu_typename(pc);
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size_t size = object_type_get_instance_size(typename);
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Error *local_err = NULL;
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void *obj;
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int i, j;
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char name[32];
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Object *xi;
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xi = object_property_get_link(OBJECT(dev), "xics", &local_err);
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if (!xi) {
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error_setg(errp, "%s: required link 'xics' not found: %s",
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__func__, error_get_pretty(local_err));
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return;
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}
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pc->threads = g_malloc0(size * cc->nr_threads);
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for (i = 0; i < cc->nr_threads; i++) {
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obj = pc->threads + i * size;
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object_initialize(obj, size, typename);
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snprintf(name, sizeof(name), "thread[%d]", i);
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object_property_add_child(OBJECT(pc), name, obj, &local_err);
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object_property_add_alias(obj, "core-pir", OBJECT(pc),
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"pir", &local_err);
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if (local_err) {
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goto err;
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}
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object_unref(obj);
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}
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for (j = 0; j < cc->nr_threads; j++) {
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obj = pc->threads + j * size;
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pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err);
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if (local_err) {
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goto err;
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}
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}
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snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
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pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops,
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pc, name, PNV_XSCOM_EX_CORE_SIZE);
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return;
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err:
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while (--i >= 0) {
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obj = pc->threads + i * size;
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object_unparent(obj);
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}
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g_free(pc->threads);
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error_propagate(errp, local_err);
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}
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static Property pnv_core_properties[] = {
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DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pnv_core_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = pnv_core_realize;
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dc->props = pnv_core_properties;
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}
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#define DEFINE_PNV_CORE_TYPE(cpu_model) \
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{ \
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.parent = TYPE_PNV_CORE, \
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.name = PNV_CORE_TYPE_NAME(cpu_model), \
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}
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static const TypeInfo pnv_core_infos[] = {
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{
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.name = TYPE_PNV_CORE,
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.parent = TYPE_CPU_CORE,
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.instance_size = sizeof(PnvCore),
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.class_size = sizeof(PnvCoreClass),
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.class_init = pnv_core_class_init,
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.abstract = true,
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},
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DEFINE_PNV_CORE_TYPE("power8e_v2.1"),
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DEFINE_PNV_CORE_TYPE("power8_v2.0"),
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DEFINE_PNV_CORE_TYPE("power8nvl_v1.0"),
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DEFINE_PNV_CORE_TYPE("power9_v2.0"),
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};
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DEFINE_TYPES(pnv_core_infos)
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