Modify the pre_save method on VMStateDescription to return an int rather than void so that it potentially can fail. Changed zillions of devices to make them return 0; the only case I've made it return non-0 is hw/intc/s390_flic_kvm.c that already had an error_report/return case. Note: If you add an error exit in your pre_save you must emit an error_report to say why. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20170925112917.21340-2-dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
495 lines
12 KiB
C
495 lines
12 KiB
C
/*
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* Xilinx Zynq cadence TTC model
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*
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* Copyright (c) 2011 Xilinx Inc.
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* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
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* Copyright (c) 2012 PetaLogix Pty Ltd.
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* Written By Haibing Ma
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* M. Habib
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#ifdef CADENCE_TTC_ERR_DEBUG
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#define DB_PRINT(...) do { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \
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} while (0);
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#else
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#define DB_PRINT(...)
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#endif
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#define COUNTER_INTR_IV 0x00000001
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#define COUNTER_INTR_M1 0x00000002
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#define COUNTER_INTR_M2 0x00000004
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#define COUNTER_INTR_M3 0x00000008
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#define COUNTER_INTR_OV 0x00000010
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#define COUNTER_INTR_EV 0x00000020
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#define COUNTER_CTRL_DIS 0x00000001
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#define COUNTER_CTRL_INT 0x00000002
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#define COUNTER_CTRL_DEC 0x00000004
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#define COUNTER_CTRL_MATCH 0x00000008
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#define COUNTER_CTRL_RST 0x00000010
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#define CLOCK_CTRL_PS_EN 0x00000001
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#define CLOCK_CTRL_PS_V 0x0000001e
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typedef struct {
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QEMUTimer *timer;
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int freq;
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uint32_t reg_clock;
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uint32_t reg_count;
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uint32_t reg_value;
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uint16_t reg_interval;
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uint16_t reg_match[3];
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uint32_t reg_intr;
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uint32_t reg_intr_en;
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uint32_t reg_event_ctrl;
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uint32_t reg_event;
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uint64_t cpu_time;
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unsigned int cpu_time_valid;
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qemu_irq irq;
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} CadenceTimerState;
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#define TYPE_CADENCE_TTC "cadence_ttc"
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#define CADENCE_TTC(obj) \
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OBJECT_CHECK(CadenceTTCState, (obj), TYPE_CADENCE_TTC)
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typedef struct CadenceTTCState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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CadenceTimerState timer[3];
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} CadenceTTCState;
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static void cadence_timer_update(CadenceTimerState *s)
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{
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qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
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}
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static CadenceTimerState *cadence_timer_from_addr(void *opaque,
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hwaddr offset)
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{
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unsigned int index;
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CadenceTTCState *s = (CadenceTTCState *)opaque;
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index = (offset >> 2) % 3;
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return &s->timer[index];
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}
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static uint64_t cadence_timer_get_ns(CadenceTimerState *s, uint64_t timer_steps)
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{
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/* timer_steps has max value of 0x100000000. double check it
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* (or overflow can happen below) */
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assert(timer_steps <= 1ULL << 32);
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uint64_t r = timer_steps * 1000000000ULL;
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if (s->reg_clock & CLOCK_CTRL_PS_EN) {
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r >>= 16 - (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
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} else {
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r >>= 16;
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}
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r /= (uint64_t)s->freq;
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return r;
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}
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static uint64_t cadence_timer_get_steps(CadenceTimerState *s, uint64_t ns)
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{
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uint64_t to_divide = 1000000000ULL;
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uint64_t r = ns;
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/* for very large intervals (> 8s) do some division first to stop
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* overflow (costs some prescision) */
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while (r >= 8ULL << 30 && to_divide > 1) {
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r /= 1000;
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to_divide /= 1000;
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}
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r <<= 16;
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/* keep early-dividing as needed */
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while (r >= 8ULL << 30 && to_divide > 1) {
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r /= 1000;
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to_divide /= 1000;
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}
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r *= (uint64_t)s->freq;
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if (s->reg_clock & CLOCK_CTRL_PS_EN) {
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r /= 1 << (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
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}
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r /= to_divide;
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return r;
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}
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/* determine if x is in between a and b, exclusive of a, inclusive of b */
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static inline int64_t is_between(int64_t x, int64_t a, int64_t b)
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{
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if (a < b) {
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return x > a && x <= b;
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}
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return x < a && x >= b;
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}
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static void cadence_timer_run(CadenceTimerState *s)
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{
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int i;
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int64_t event_interval, next_value;
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assert(s->cpu_time_valid); /* cadence_timer_sync must be called first */
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if (s->reg_count & COUNTER_CTRL_DIS) {
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s->cpu_time_valid = 0;
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return;
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}
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{ /* figure out what's going to happen next (rollover or match) */
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int64_t interval = (uint64_t)((s->reg_count & COUNTER_CTRL_INT) ?
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(int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;
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next_value = (s->reg_count & COUNTER_CTRL_DEC) ? -1ULL : interval;
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for (i = 0; i < 3; ++i) {
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int64_t cand = (uint64_t)s->reg_match[i] << 16;
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if (is_between(cand, (uint64_t)s->reg_value, next_value)) {
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next_value = cand;
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}
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}
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}
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DB_PRINT("next timer event value: %09llx\n",
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(unsigned long long)next_value);
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event_interval = next_value - (int64_t)s->reg_value;
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event_interval = (event_interval < 0) ? -event_interval : event_interval;
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timer_mod(s->timer, s->cpu_time +
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cadence_timer_get_ns(s, event_interval));
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}
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static void cadence_timer_sync(CadenceTimerState *s)
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{
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int i;
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int64_t r, x;
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int64_t interval = ((s->reg_count & COUNTER_CTRL_INT) ?
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(int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;
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uint64_t old_time = s->cpu_time;
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s->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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DB_PRINT("cpu time: %lld ns\n", (long long)old_time);
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if (!s->cpu_time_valid || old_time == s->cpu_time) {
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s->cpu_time_valid = 1;
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return;
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}
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r = (int64_t)cadence_timer_get_steps(s, s->cpu_time - old_time);
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x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r);
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for (i = 0; i < 3; ++i) {
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int64_t m = (int64_t)s->reg_match[i] << 16;
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if (m > interval) {
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continue;
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}
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/* check to see if match event has occurred. check m +/- interval
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* to account for match events in wrap around cases */
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if (is_between(m, s->reg_value, x) ||
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is_between(m + interval, s->reg_value, x) ||
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is_between(m - interval, s->reg_value, x)) {
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s->reg_intr |= (2 << i);
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}
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}
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if ((x < 0) || (x >= interval)) {
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s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ?
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COUNTER_INTR_IV : COUNTER_INTR_OV;
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}
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while (x < 0) {
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x += interval;
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}
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s->reg_value = (uint32_t)(x % interval);
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cadence_timer_update(s);
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}
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static void cadence_timer_tick(void *opaque)
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{
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CadenceTimerState *s = opaque;
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DB_PRINT("\n");
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cadence_timer_sync(s);
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cadence_timer_run(s);
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}
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static uint32_t cadence_ttc_read_imp(void *opaque, hwaddr offset)
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{
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CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
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uint32_t value;
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cadence_timer_sync(s);
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cadence_timer_run(s);
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switch (offset) {
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case 0x00: /* clock control */
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case 0x04:
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case 0x08:
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return s->reg_clock;
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case 0x0c: /* counter control */
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case 0x10:
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case 0x14:
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return s->reg_count;
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case 0x18: /* counter value */
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case 0x1c:
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case 0x20:
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return (uint16_t)(s->reg_value >> 16);
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case 0x24: /* reg_interval counter */
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case 0x28:
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case 0x2c:
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return s->reg_interval;
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case 0x30: /* match 1 counter */
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case 0x34:
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case 0x38:
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return s->reg_match[0];
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case 0x3c: /* match 2 counter */
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case 0x40:
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case 0x44:
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return s->reg_match[1];
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case 0x48: /* match 3 counter */
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case 0x4c:
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case 0x50:
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return s->reg_match[2];
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case 0x54: /* interrupt register */
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case 0x58:
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case 0x5c:
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/* cleared after read */
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value = s->reg_intr;
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s->reg_intr = 0;
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cadence_timer_update(s);
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return value;
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case 0x60: /* interrupt enable */
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case 0x64:
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case 0x68:
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return s->reg_intr_en;
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case 0x6c:
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case 0x70:
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case 0x74:
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return s->reg_event_ctrl;
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case 0x78:
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case 0x7c:
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case 0x80:
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return s->reg_event;
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default:
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return 0;
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}
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}
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static uint64_t cadence_ttc_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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uint32_t ret = cadence_ttc_read_imp(opaque, offset);
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DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)ret);
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return ret;
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}
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static void cadence_ttc_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
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DB_PRINT("addr: %08x data %08x\n", (unsigned)offset, (unsigned)value);
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cadence_timer_sync(s);
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switch (offset) {
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case 0x00: /* clock control */
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case 0x04:
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case 0x08:
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s->reg_clock = value & 0x3F;
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break;
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case 0x0c: /* counter control */
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case 0x10:
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case 0x14:
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if (value & COUNTER_CTRL_RST) {
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s->reg_value = 0;
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}
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s->reg_count = value & 0x3f & ~COUNTER_CTRL_RST;
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break;
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case 0x24: /* interval register */
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case 0x28:
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case 0x2c:
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s->reg_interval = value & 0xffff;
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break;
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case 0x30: /* match register */
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case 0x34:
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case 0x38:
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s->reg_match[0] = value & 0xffff;
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break;
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case 0x3c: /* match register */
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case 0x40:
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case 0x44:
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s->reg_match[1] = value & 0xffff;
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break;
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case 0x48: /* match register */
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case 0x4c:
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case 0x50:
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s->reg_match[2] = value & 0xffff;
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break;
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case 0x54: /* interrupt register */
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case 0x58:
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case 0x5c:
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break;
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case 0x60: /* interrupt enable */
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case 0x64:
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case 0x68:
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s->reg_intr_en = value & 0x3f;
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break;
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case 0x6c: /* event control */
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case 0x70:
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case 0x74:
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s->reg_event_ctrl = value & 0x07;
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break;
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default:
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return;
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}
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cadence_timer_run(s);
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cadence_timer_update(s);
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}
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static const MemoryRegionOps cadence_ttc_ops = {
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.read = cadence_ttc_read,
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.write = cadence_ttc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void cadence_timer_reset(CadenceTimerState *s)
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{
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s->reg_count = 0x21;
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}
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static void cadence_timer_init(uint32_t freq, CadenceTimerState *s)
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{
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memset(s, 0, sizeof(CadenceTimerState));
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s->freq = freq;
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cadence_timer_reset(s);
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s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cadence_timer_tick, s);
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}
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static void cadence_ttc_init(Object *obj)
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{
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CadenceTTCState *s = CADENCE_TTC(obj);
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int i;
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for (i = 0; i < 3; ++i) {
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cadence_timer_init(133000000, &s->timer[i]);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->timer[i].irq);
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}
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memory_region_init_io(&s->iomem, obj, &cadence_ttc_ops, s,
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"timer", 0x1000);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
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}
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static int cadence_timer_pre_save(void *opaque)
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{
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cadence_timer_sync((CadenceTimerState *)opaque);
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return 0;
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}
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static int cadence_timer_post_load(void *opaque, int version_id)
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{
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CadenceTimerState *s = opaque;
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s->cpu_time_valid = 0;
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cadence_timer_sync(s);
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cadence_timer_run(s);
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cadence_timer_update(s);
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return 0;
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}
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static const VMStateDescription vmstate_cadence_timer = {
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.name = "cadence_timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = cadence_timer_pre_save,
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.post_load = cadence_timer_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(reg_clock, CadenceTimerState),
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VMSTATE_UINT32(reg_count, CadenceTimerState),
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VMSTATE_UINT32(reg_value, CadenceTimerState),
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VMSTATE_UINT16(reg_interval, CadenceTimerState),
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VMSTATE_UINT16_ARRAY(reg_match, CadenceTimerState, 3),
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VMSTATE_UINT32(reg_intr, CadenceTimerState),
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VMSTATE_UINT32(reg_intr_en, CadenceTimerState),
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VMSTATE_UINT32(reg_event_ctrl, CadenceTimerState),
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VMSTATE_UINT32(reg_event, CadenceTimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_cadence_ttc = {
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.name = "cadence_TTC",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(timer, CadenceTTCState, 3, 0,
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vmstate_cadence_timer,
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CadenceTimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void cadence_ttc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_cadence_ttc;
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}
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static const TypeInfo cadence_ttc_info = {
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.name = TYPE_CADENCE_TTC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(CadenceTTCState),
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.instance_init = cadence_ttc_init,
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.class_init = cadence_ttc_class_init,
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};
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static void cadence_ttc_register_types(void)
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{
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type_register_static(&cadence_ttc_info);
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}
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type_init(cadence_ttc_register_types)
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