Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add IP3 delivery as well, because Loongson-3 based machine use both IRQ2 (CPU's IP2) and IRQ3 (CPU's IP3). Signed-off-by: Huacai Chen <chenhc@lemote.com> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <1588501221-1205-4-git-send-email-chenhc@lemote.com> |
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addr.c | ||
boston.c | ||
cps.c | ||
fuloong2e.c | ||
gt64xxx_pci.c | ||
jazz.c | ||
Kconfig | ||
Makefile.objs | ||
malta.c | ||
mips_int.c | ||
mipssim.c | ||
r4k.c | ||
trace-events |