qemu-patch-raspberry4/target
Anup Patel ee79e7cd47 riscv: Fix Stage2 SV32 page table walk
As-per RISC-V H-Extension v0.5 draft, the Stage2 SV32 page table has
12bits of VPN[1] and 10bits of VPN[0]. The additional 2bits in VPN[1]
is required to handle the 34bit intermediate physical address coming
from Stage1 SV32 page table. The 12bits of VPN[1] implies that Stage2
SV32 level-0 page table will be 16KB in size with total 4096 enteries
where each entry maps 4MB of memory (same as Stage1 SV32 page table).

The get_physical_address() function is broken for Stage2 SV32 level-0
page table because it incorrectly computes output physical address for
Stage2 SV32 level-0 page table entry.

The root cause of the issue is that get_physical_address() uses the
"widened" variable to compute level-0 physical address mapping which
changes level-0 mapping size (instead of 4MB). We should use the
"widened" variable only for computing index of Stage2 SV32 level-0
page table.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200330082724.120444-1-anup.patel@wdc.com
Message-Id: <20200330082724.120444-1-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-04-29 13:16:37 -07:00
..
alpha x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
arm target/arm: Fix ID_MMFR4 value on AArch64 'max' CPU 2020-04-22 16:18:31 +01:00
cris x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
hppa x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
i386 various: Remove suspicious '\' character outside of #define in C code 2020-04-29 08:01:51 +02:00
lm32 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
m68k target/m68k/helper: Fix m68k_fpu_gdb_get_reg() use of GByteArray 2020-04-15 11:38:23 +01:00
microblaze various: Remove suspicious '\' character outside of #define in C code 2020-04-29 08:01:51 +02:00
mips target/mips: Fix loongson multimedia condition instructions 2020-03-28 14:09:45 -07:00
moxie cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
nios2 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
openrisc x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
ppc various: Remove suspicious '\' character outside of #define in C code 2020-04-29 08:01:51 +02:00
riscv riscv: Fix Stage2 SV32 page table walk 2020-04-29 13:16:37 -07:00
rx target/rx/translate: Add missing fall through comment 2020-04-07 18:45:54 -07:00
s390x s390x: kvm: Fix number of cpu reports for stsi 3.2.2 2020-04-02 11:44:17 +02:00
sh4 gdbstub: Introduce gdb_get_float32() to get 32-bit float registers 2020-04-15 11:38:23 +01:00
sparc x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
tilegx cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
tricore cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
unicore32 tcg: Search includes from the project root source directory 2020-01-15 15:13:10 -10:00
xtensa gdbstub: Do not use memset() on GByteArray 2020-04-15 11:38:23 +01:00