637 lines
19 KiB
C
637 lines
19 KiB
C
/*
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* TI OMAP general purpose memory controller emulation.
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*
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* Copyright (C) 2007-2009 Nokia Corporation
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* Original code written by Andrzej Zaborowski <andrew@openedhand.com>
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* Enhancements for OMAP3 and NAND support written by Juha Riihimäki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) any later version of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h"
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#include "flash.h"
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#include "omap.h"
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#include "memory.h"
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#include "exec-memory.h"
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/* General-Purpose Memory Controller */
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struct omap_gpmc_s {
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qemu_irq irq;
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qemu_irq drq;
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MemoryRegion iomem;
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int accept_256;
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uint8_t revision;
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uint8_t sysconfig;
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uint16_t irqst;
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uint16_t irqen;
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uint16_t timeout;
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uint16_t config;
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struct omap_gpmc_cs_file_s {
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uint32_t config[7];
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MemoryRegion *iomem;
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MemoryRegion container;
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MemoryRegion nandiomem;
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DeviceState *dev;
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} cs_file[8];
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int ecc_cs;
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int ecc_ptr;
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uint32_t ecc_cfg;
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ECCState ecc[9];
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struct prefetch {
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uint32_t config1; /* GPMC_PREFETCH_CONFIG1 */
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uint32_t transfercount; /* GPMC_PREFETCH_CONFIG2:TRANSFERCOUNT */
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int startengine; /* GPMC_PREFETCH_CONTROL:STARTENGINE */
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int fifopointer; /* GPMC_PREFETCH_STATUS:FIFOPOINTER */
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int count; /* GPMC_PREFETCH_STATUS:COUNTVALUE */
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} prefetch;
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};
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#define OMAP_GPMC_8BIT 0
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#define OMAP_GPMC_16BIT 1
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#define OMAP_GPMC_NOR 0
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#define OMAP_GPMC_NAND 2
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static int omap_gpmc_devtype(struct omap_gpmc_cs_file_s *f)
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{
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return (f->config[0] >> 10) & 3;
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}
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static int omap_gpmc_devsize(struct omap_gpmc_cs_file_s *f)
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{
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/* devsize field is really 2 bits but we ignore the high
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* bit to ensure consistent behaviour if the guest sets
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* it (values 2 and 3 are reserved in the TRM)
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*/
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return (f->config[0] >> 12) & 1;
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}
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static void omap_gpmc_int_update(struct omap_gpmc_s *s)
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{
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qemu_set_irq(s->irq, s->irqen & s->irqst);
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}
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/* Access functions for when a NAND-like device is mapped into memory:
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* all addresses in the region behave like accesses to the relevant
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* GPMC_NAND_DATA_i register (which is actually implemented to call these)
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*/
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static uint64_t omap_nand_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
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uint64_t v;
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nand_setpins(f->dev, 0, 0, 0, 1, 0);
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switch (omap_gpmc_devsize(f)) {
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case OMAP_GPMC_8BIT:
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v = nand_getio(f->dev);
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if (size == 1) {
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return v;
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}
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v |= (nand_getio(f->dev) << 8);
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if (size == 2) {
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return v;
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}
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v |= (nand_getio(f->dev) << 16);
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v |= (nand_getio(f->dev) << 24);
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return v;
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case OMAP_GPMC_16BIT:
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v = nand_getio(f->dev);
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if (size == 1) {
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/* 8 bit read from 16 bit device : probably a guest bug */
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return v & 0xff;
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}
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if (size == 2) {
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return v;
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}
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v |= (nand_getio(f->dev) << 16);
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return v;
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default:
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abort();
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}
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}
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static void omap_nand_setio(DeviceState *dev, uint64_t value,
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int nandsize, int size)
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{
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/* Write the specified value to the NAND device, respecting
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* both size of the NAND device and size of the write access.
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*/
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switch (nandsize) {
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case OMAP_GPMC_8BIT:
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switch (size) {
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case 1:
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nand_setio(dev, value & 0xff);
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break;
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case 2:
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nand_setio(dev, value & 0xff);
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nand_setio(dev, (value >> 8) & 0xff);
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break;
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case 4:
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default:
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nand_setio(dev, value & 0xff);
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nand_setio(dev, (value >> 8) & 0xff);
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nand_setio(dev, (value >> 16) & 0xff);
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nand_setio(dev, (value >> 24) & 0xff);
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break;
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}
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case OMAP_GPMC_16BIT:
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switch (size) {
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case 1:
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/* writing to a 16bit device with 8bit access is probably a guest
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* bug; pass the value through anyway.
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*/
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case 2:
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nand_setio(dev, value & 0xffff);
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break;
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case 4:
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default:
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nand_setio(dev, value & 0xffff);
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nand_setio(dev, (value >> 16) & 0xffff);
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break;
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}
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}
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}
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static void omap_nand_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
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nand_setpins(f->dev, 0, 0, 0, 1, 0);
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omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
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}
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static const MemoryRegionOps omap_nand_ops = {
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.read = omap_nand_read,
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.write = omap_nand_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static MemoryRegion *omap_gpmc_cs_memregion(struct omap_gpmc_s *s, int cs)
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{
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/* Return the MemoryRegion* to map/unmap for this chipselect */
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struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
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if (omap_gpmc_devtype(f) == OMAP_GPMC_NOR) {
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return f->iomem;
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}
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return &f->nandiomem;
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}
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static void omap_gpmc_cs_map(struct omap_gpmc_s *s, int cs)
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{
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struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
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uint32_t mask = (f->config[6] >> 8) & 0xf;
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uint32_t base = f->config[6] & 0x3f;
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uint32_t size;
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if (!f->iomem && !f->dev) {
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return;
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}
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if (!(f->config[6] & (1 << 6))) {
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/* Do nothing unless CSVALID */
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return;
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}
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/* TODO: check for overlapping regions and report access errors */
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if (mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf
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&& !(s->accept_256 && !mask)) {
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fprintf(stderr, "%s: invalid chip-select mask address (0x%x)\n",
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__func__, mask);
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}
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base <<= 24;
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size = (0x0fffffff & ~(mask << 24)) + 1;
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/* TODO: rather than setting the size of the mapping (which should be
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* constant), the mask should cause wrapping of the address space, so
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* that the same memory becomes accessible at every <i>size</i> bytes
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* starting from <i>base</i>. */
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memory_region_init(&f->container, "omap-gpmc-file", size);
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memory_region_add_subregion(&f->container, 0,
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omap_gpmc_cs_memregion(s, cs));
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memory_region_add_subregion(get_system_memory(), base,
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&f->container);
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}
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static void omap_gpmc_cs_unmap(struct omap_gpmc_s *s, int cs)
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{
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struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
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if (!(f->config[6] & (1 << 6))) {
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/* Do nothing unless CSVALID */
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return;
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}
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if (!f->iomem && !f->dev) {
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return;
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}
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memory_region_del_subregion(get_system_memory(), &f->container);
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memory_region_del_subregion(&f->container, omap_gpmc_cs_memregion(s, cs));
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memory_region_destroy(&f->container);
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}
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void omap_gpmc_reset(struct omap_gpmc_s *s)
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{
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int i;
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s->sysconfig = 0;
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s->irqst = 0;
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s->irqen = 0;
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omap_gpmc_int_update(s);
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s->timeout = 0;
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s->config = 0xa00;
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s->prefetch.config1 = 0x00004000;
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s->prefetch.transfercount = 0x00000000;
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s->prefetch.startengine = 0;
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s->prefetch.fifopointer = 0;
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s->prefetch.count = 0;
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for (i = 0; i < 8; i ++) {
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omap_gpmc_cs_unmap(s, i);
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s->cs_file[i].config[1] = 0x101001;
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s->cs_file[i].config[2] = 0x020201;
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s->cs_file[i].config[3] = 0x10031003;
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s->cs_file[i].config[4] = 0x10f1111;
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s->cs_file[i].config[5] = 0;
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s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
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s->cs_file[i].config[6] = 0xf00;
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/* In theory we could probe attached devices for some CFG1
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* bits here, but we just retain them across resets as they
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* were set initially by omap_gpmc_attach().
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*/
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if (i == 0) {
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s->cs_file[i].config[0] &= 0x00433e00;
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s->cs_file[i].config[6] |= 1 << 6; /* CSVALID */
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omap_gpmc_cs_map(s, i);
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} else {
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s->cs_file[i].config[0] &= 0x00403c00;
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}
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}
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s->ecc_cs = 0;
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s->ecc_ptr = 0;
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s->ecc_cfg = 0x3fcff000;
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for (i = 0; i < 9; i ++)
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ecc_reset(&s->ecc[i]);
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}
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static int gpmc_wordaccess_only(target_phys_addr_t addr)
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{
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/* Return true if the register offset is to a register that
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* only permits word width accesses.
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* Non-word accesses are only OK for GPMC_NAND_DATA/ADDRESS/COMMAND
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* for any chipselect.
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*/
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if (addr >= 0x60 && addr <= 0x1d4) {
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int cs = (addr - 0x60) / 0x30;
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addr -= cs * 0x30;
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if (addr >= 0x7c && addr < 0x88) {
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/* GPMC_NAND_COMMAND, GPMC_NAND_ADDRESS, GPMC_NAND_DATA */
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return 0;
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}
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}
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return 1;
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}
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static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
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int cs;
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struct omap_gpmc_cs_file_s *f;
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if (size != 4 && gpmc_wordaccess_only(addr)) {
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return omap_badwidth_read32(opaque, addr);
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}
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switch (addr) {
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case 0x000: /* GPMC_REVISION */
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return s->revision;
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case 0x010: /* GPMC_SYSCONFIG */
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return s->sysconfig;
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case 0x014: /* GPMC_SYSSTATUS */
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return 1; /* RESETDONE */
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case 0x018: /* GPMC_IRQSTATUS */
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return s->irqst;
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case 0x01c: /* GPMC_IRQENABLE */
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return s->irqen;
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case 0x040: /* GPMC_TIMEOUT_CONTROL */
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return s->timeout;
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case 0x044: /* GPMC_ERR_ADDRESS */
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case 0x048: /* GPMC_ERR_TYPE */
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return 0;
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case 0x050: /* GPMC_CONFIG */
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return s->config;
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case 0x054: /* GPMC_STATUS */
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return 0x001;
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case 0x060 ... 0x1d4:
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cs = (addr - 0x060) / 0x30;
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addr -= cs * 0x30;
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f = s->cs_file + cs;
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switch (addr) {
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case 0x60: /* GPMC_CONFIG1 */
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return f->config[0];
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case 0x64: /* GPMC_CONFIG2 */
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return f->config[1];
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case 0x68: /* GPMC_CONFIG3 */
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return f->config[2];
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case 0x6c: /* GPMC_CONFIG4 */
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return f->config[3];
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case 0x70: /* GPMC_CONFIG5 */
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return f->config[4];
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case 0x74: /* GPMC_CONFIG6 */
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return f->config[5];
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case 0x78: /* GPMC_CONFIG7 */
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return f->config[6];
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case 0x84 ... 0x87: /* GPMC_NAND_DATA */
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if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
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return omap_nand_read(f, 0, size);
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}
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return 0;
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}
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break;
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case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
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return s->prefetch.config1;
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case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
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return s->prefetch.transfercount;
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case 0x1ec: /* GPMC_PREFETCH_CONTROL */
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return s->prefetch.startengine;
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case 0x1f0: /* GPMC_PREFETCH_STATUS */
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return (s->prefetch.fifopointer << 24) |
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((s->prefetch.fifopointer >=
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((s->prefetch.config1 >> 8) & 0x7f) ? 1 : 0) << 16) |
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s->prefetch.count;
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case 0x1f4: /* GPMC_ECC_CONFIG */
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return s->ecc_cs;
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case 0x1f8: /* GPMC_ECC_CONTROL */
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return s->ecc_ptr;
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case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
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return s->ecc_cfg;
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case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
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cs = (addr & 0x1f) >> 2;
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/* TODO: check correctness */
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return
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((s->ecc[cs].cp & 0x07) << 0) |
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((s->ecc[cs].cp & 0x38) << 13) |
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((s->ecc[cs].lp[0] & 0x1ff) << 3) |
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((s->ecc[cs].lp[1] & 0x1ff) << 19);
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case 0x230: /* GPMC_TESTMODE_CTRL */
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return 0;
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case 0x234: /* GPMC_PSA_LSB */
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case 0x238: /* GPMC_PSA_MSB */
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return 0x00000000;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
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int cs;
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struct omap_gpmc_cs_file_s *f;
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if (size != 4 && gpmc_wordaccess_only(addr)) {
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return omap_badwidth_write32(opaque, addr, value);
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}
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switch (addr) {
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case 0x000: /* GPMC_REVISION */
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case 0x014: /* GPMC_SYSSTATUS */
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case 0x054: /* GPMC_STATUS */
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case 0x1f0: /* GPMC_PREFETCH_STATUS */
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case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
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case 0x234: /* GPMC_PSA_LSB */
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case 0x238: /* GPMC_PSA_MSB */
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OMAP_RO_REG(addr);
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break;
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case 0x010: /* GPMC_SYSCONFIG */
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if ((value >> 3) == 0x3)
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fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
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__FUNCTION__, value >> 3);
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if (value & 2)
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omap_gpmc_reset(s);
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s->sysconfig = value & 0x19;
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break;
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case 0x018: /* GPMC_IRQSTATUS */
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s->irqen &= ~value;
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omap_gpmc_int_update(s);
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break;
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case 0x01c: /* GPMC_IRQENABLE */
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s->irqen = value & 0xf03;
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omap_gpmc_int_update(s);
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break;
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case 0x040: /* GPMC_TIMEOUT_CONTROL */
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s->timeout = value & 0x1ff1;
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break;
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case 0x044: /* GPMC_ERR_ADDRESS */
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case 0x048: /* GPMC_ERR_TYPE */
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break;
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case 0x050: /* GPMC_CONFIG */
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s->config = value & 0xf13;
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break;
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case 0x060 ... 0x1d4:
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cs = (addr - 0x060) / 0x30;
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addr -= cs * 0x30;
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f = s->cs_file + cs;
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switch (addr) {
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case 0x60: /* GPMC_CONFIG1 */
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f->config[0] = value & 0xffef3e13;
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break;
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case 0x64: /* GPMC_CONFIG2 */
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f->config[1] = value & 0x001f1f8f;
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break;
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case 0x68: /* GPMC_CONFIG3 */
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f->config[2] = value & 0x001f1f8f;
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break;
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case 0x6c: /* GPMC_CONFIG4 */
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f->config[3] = value & 0x1f8f1f8f;
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break;
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case 0x70: /* GPMC_CONFIG5 */
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f->config[4] = value & 0x0f1f1f1f;
|
|
break;
|
|
case 0x74: /* GPMC_CONFIG6 */
|
|
f->config[5] = value & 0x00000fcf;
|
|
break;
|
|
case 0x78: /* GPMC_CONFIG7 */
|
|
if ((f->config[6] ^ value) & 0xf7f) {
|
|
omap_gpmc_cs_unmap(s, cs);
|
|
f->config[6] = value & 0x00000f7f;
|
|
omap_gpmc_cs_map(s, cs);
|
|
}
|
|
break;
|
|
case 0x7c ... 0x7f: /* GPMC_NAND_COMMAND */
|
|
if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
|
|
nand_setpins(f->dev, 1, 0, 0, 1, 0); /* CLE */
|
|
omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
|
|
}
|
|
break;
|
|
case 0x80 ... 0x83: /* GPMC_NAND_ADDRESS */
|
|
if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
|
|
nand_setpins(f->dev, 0, 1, 0, 1, 0); /* ALE */
|
|
omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
|
|
}
|
|
break;
|
|
case 0x84 ... 0x87: /* GPMC_NAND_DATA */
|
|
if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
|
|
omap_nand_write(f, 0, value, size);
|
|
}
|
|
break;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
break;
|
|
|
|
case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
|
|
s->prefetch.config1 = value & 0x7f8f7fbf;
|
|
/* TODO: update interrupts, fifos, dmas */
|
|
break;
|
|
|
|
case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
|
|
s->prefetch.transfercount = value & 0x3fff;
|
|
break;
|
|
|
|
case 0x1ec: /* GPMC_PREFETCH_CONTROL */
|
|
s->prefetch.startengine = value & 1;
|
|
if (s->prefetch.startengine) {
|
|
if (s->prefetch.config1 & 1) {
|
|
s->prefetch.fifopointer = 0x40;
|
|
} else {
|
|
s->prefetch.fifopointer = 0x00;
|
|
}
|
|
}
|
|
/* TODO: start */
|
|
break;
|
|
|
|
case 0x1f4: /* GPMC_ECC_CONFIG */
|
|
s->ecc_cs = 0x8f;
|
|
break;
|
|
case 0x1f8: /* GPMC_ECC_CONTROL */
|
|
if (value & (1 << 8))
|
|
for (cs = 0; cs < 9; cs ++)
|
|
ecc_reset(&s->ecc[cs]);
|
|
s->ecc_ptr = value & 0xf;
|
|
if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
|
|
s->ecc_ptr = 0;
|
|
s->ecc_cs &= ~1;
|
|
}
|
|
break;
|
|
case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
|
|
s->ecc_cfg = value & 0x3fcff1ff;
|
|
break;
|
|
case 0x230: /* GPMC_TESTMODE_CTRL */
|
|
if (value & 7)
|
|
fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
|
|
break;
|
|
|
|
default:
|
|
bad_reg:
|
|
OMAP_BAD_REG(addr);
|
|
return;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps omap_gpmc_ops = {
|
|
.read = omap_gpmc_read,
|
|
.write = omap_gpmc_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
|
|
target_phys_addr_t base,
|
|
qemu_irq irq, qemu_irq drq)
|
|
{
|
|
int cs;
|
|
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
|
|
g_malloc0(sizeof(struct omap_gpmc_s));
|
|
|
|
memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
|
|
memory_region_add_subregion(get_system_memory(), base, &s->iomem);
|
|
|
|
s->irq = irq;
|
|
s->drq = drq;
|
|
s->accept_256 = cpu_is_omap3630(mpu);
|
|
s->revision = cpu_class_omap3(mpu) ? 0x50 : 0x20;
|
|
omap_gpmc_reset(s);
|
|
|
|
/* We have to register a different IO memory handler for each
|
|
* chip select region in case a NAND device is mapped there. We
|
|
* make the region the worst-case size of 256MB and rely on the
|
|
* container memory region in cs_map to chop it down to the actual
|
|
* guest-requested size.
|
|
*/
|
|
for (cs = 0; cs < 8; cs++) {
|
|
memory_region_init_io(&s->cs_file[cs].nandiomem,
|
|
&omap_nand_ops,
|
|
&s->cs_file[cs],
|
|
"omap-nand",
|
|
256 * 1024 * 1024);
|
|
}
|
|
return s;
|
|
}
|
|
|
|
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem)
|
|
{
|
|
struct omap_gpmc_cs_file_s *f;
|
|
assert(iomem);
|
|
|
|
if (cs < 0 || cs >= 8) {
|
|
fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
|
|
exit(-1);
|
|
}
|
|
f = &s->cs_file[cs];
|
|
|
|
omap_gpmc_cs_unmap(s, cs);
|
|
f->config[0] &= ~(0xf << 10);
|
|
f->iomem = iomem;
|
|
omap_gpmc_cs_map(s, cs);
|
|
}
|
|
|
|
void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand)
|
|
{
|
|
struct omap_gpmc_cs_file_s *f;
|
|
assert(nand);
|
|
|
|
if (cs < 0 || cs >= 8) {
|
|
fprintf(stderr, "%s: bad chip-select %i\n", __func__, cs);
|
|
exit(-1);
|
|
}
|
|
f = &s->cs_file[cs];
|
|
|
|
omap_gpmc_cs_unmap(s, cs);
|
|
f->config[0] &= ~(0xf << 10);
|
|
f->config[0] |= (OMAP_GPMC_NAND << 10);
|
|
f->dev = nand;
|
|
if (nand_getbuswidth(f->dev) == 16) {
|
|
f->config[0] |= OMAP_GPMC_16BIT << 12;
|
|
}
|
|
omap_gpmc_cs_map(s, cs);
|
|
}
|